X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsbc8641d.h;h=1008812b711ac9d7986196093820ddc596ffbf9c;hb=c1b7c70083fc8d0bb77db20dd47bb6c988f3dc67;hp=001294575822baa9e8fb81c31a5bcc6d80ace346;hpb=90665e3d97948000f98846ded37c921c7ae67dd7;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 0012945..1008812 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -311,18 +311,22 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS	0xe2000000
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
+#define CONFIG_SYS_PCI1_IO_VIRT	CONFIG_SYS_PCI1_IO_BUS
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/* 16M */
 
-#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BUS
+#define CONFIG_SYS_PCI2_MEM_VIRT	CONFIG_SYS_PCI2_MEM_BUS
 #define CONFIG_SYS_PCI2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE	0xe3000000
-#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BASE
+#define CONFIG_SYS_PCI2_IO_BUS	0xe3000000
+#define CONFIG_SYS_PCI2_IO_PHYS	CONFIG_SYS_PCI2_IO_BUS
+#define CONFIG_SYS_PCI2_IO_VIRT	CONFIG_SYS_PCI2_IO_BUS
 #define CONFIG_SYS_PCI2_IO_SIZE	0x1000000	/* 16M */
 
 #if defined(CONFIG_PCI)
@@ -409,10 +413,10 @@
  * 0xa000_0000  512M   PCI-Express 2 Memory
  *	Changed it for operating from 0xd0000000
  */
-#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT1L	( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
 
 /*
@@ -452,10 +456,10 @@
  * 0xe300_0000  16M    PCI-Express 2 I/0
  *    Note that this is at 0xe0000000
  */
-#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT4L	( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
 
 /*