X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsbc8349.h;h=775bbe417afc57dabb745c741f9bf3fff893e1d4;hb=71da74743180c81c3af31108839b5d0e6a1aff87;hp=5b5689a34352f661d3d848e10758edffd6e8f719;hpb=0bb430c8494e26e8d258cf6957cdd39d2ce4f309;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 5b5689a..775bbe4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -1,11 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * WindRiver SBC8349 U-Boot configuration file. * Copyright (c) 2006, 2007 Wind River Systems, Inc. * * Paul Gortmaker * Based on the MPC8349EMDS config. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -19,36 +18,10 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC834x 1 /* MPC834x family */ -#define CONFIG_MPC8349 1 /* MPC8349 specific */ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ -/* - * The default if PCI isn't enabled, or if no PCI clk setting is given - * is 66MHz; this is what the board defaults to when the PCI slot is - * physically empty. The board will automatically (i.e w/o jumpers) - * clock down to 33MHz if you insert a 33MHz PCI card. - */ -#ifdef CONFIG_PCI_33M -#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ -#else /* 66M */ -#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#ifdef CONFIG_PCI_33M -#define CONFIG_SYS_CLK_FREQ 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#else /* 66M */ -#define CONFIG_SYS_CLK_FREQ 66000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#endif -#endif - -#define CONFIG_SYS_IMMR 0xE0000000 - #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00100000 @@ -120,31 +93,9 @@ /* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF806FF7 */ - - /* window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ @@ -186,80 +137,9 @@ #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ -#ifdef CONFIG_SYS_LB_SDRAM -/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ - | BR_PS_32 \ - | BR_MS_SDRAM \ - | BR_V) - /* 0xF0001861 */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - -#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ - | OR_SDRAM_XAM \ - | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ - | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ - | OR_SDRAM_EAD) - /* 0xFC006901 */ - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) -#endif - /* * Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -314,14 +194,6 @@ #if defined(CONFIG_PCI) -#define PCI_64BIT -#define PCI_ONE_PCI1 -#if defined(PCI_64BIT) -#undef PCI_ALL_PCI1 -#undef PCI_TWO_PCI1 -#undef PCI_ONE_PCI1 -#endif - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -339,7 +211,6 @@ /* * TSEC configuration */ -#define CONFIG_TSEC_ENET /* TSEC ethernet support */ #if defined(CONFIG_TSEC_ENET) @@ -406,185 +277,14 @@ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ -#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#if defined(PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) - -/* #define CONFIG_SYS_HID0_FINAL (\ - HID0_ENABLE_INSTRUCTION_CACHE |\ - HID0_ENABLE_M_BIT |\ - HID0_ENABLE_ADDRESS_BROADCAST) */ - -#define CONFIG_SYS_HID2 HID2_HBE - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* PCI @ 0x80000000 */ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT1L (0) -#define CONFIG_SYS_IBAT1U (0) -#define CONFIG_SYS_IBAT2L (0) -#define CONFIG_SYS_IBAT2U (0) #endif -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#else -#define CONFIG_SYS_IBAT3L (0) -#define CONFIG_SYS_IBAT3U (0) -#define CONFIG_SYS_IBAT4L (0) -#define CONFIG_SYS_IBAT4U (0) -#endif - -/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) - -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) - -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U -#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif @@ -599,7 +299,7 @@ #define CONFIG_HAS_ETH1 #endif -#define CONFIG_HOSTNAME SBC8349 +#define CONFIG_HOSTNAME "SBC8349" #define CONFIG_ROOTPATH "/tftpboot/rootfs" #define CONFIG_BOOTFILE "uImage"