X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsbc35_a9g20.h;h=4ba224252afc76a1ce8a346a7e73818160f22a8b;hb=1a4596601fd395f3afb8f82f3f840c5e00bdd57a;hp=f4b34775a636583534d280aca783bb084dd8771c;hpb=4b142febff71eabdb7ddbb125c7b583b24ddc434;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index f4b3477..4ba2242 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -4,74 +4,56 @@ * * Configuation settings for the Calao SBC35-A9G20 board * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM) -#define CONFIG_SBC35_A9G20 -#endif - -#define CONFIG_AT91SAM9G20 +/* SoC type is defined in boards.cfg */ +#include +#include -#if defined(CONFIG_SBC35_A9G20_NANDFLASH) +#if defined(CONFIG_SYS_USE_NANDFLASH) #define CONFIG_ENV_IS_IN_NAND #else #define CONFIG_ENV_IS_IN_EEPROM #endif -/* ARM asynchronous clock */ -#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define MACH_TYPE_SBC35_A9G20 1848 +#define CONFIG_MACH_TYPE MACH_TYPE_SBC35_A9G20 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_ARCH_CPU_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT -/* - * Hardware drivers - */ +/* GPIO */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO + +/* Serial */ #define CONFIG_ATMEL_USART -#define CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#undef CONFIG_USART3 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 /* * BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME /* * Command line configuration. @@ -84,14 +66,16 @@ #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_SOURCE -#define CONFIG_CMD_PING 1 -#define CONFIG_CMD_DHCP 1 -#define CONFIG_CMD_USB 1 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_USB /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) /* SPI EEPROM */ #define CONFIG_SPI @@ -115,7 +99,7 @@ #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ @@ -127,27 +111,26 @@ #define CONFIG_SYS_NO_FLASH 1 /* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 +#define CONFIG_MACB +#define CONFIG_RMII #define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 -#define CONFIG_MACB_SEARCH_PHY 1 +#define CONFIG_RESET_PHY_R +#define CONFIG_MACB_SEARCH_PHY /* USB */ #define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_CMD_FAT 1 +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_FAT #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x23e00000 /* Env in EEPROM, bootstrap + u-boot in NAND*/ @@ -170,8 +153,6 @@ "120M(rootfs),-(other) " \ "rw rootfstype=jffs2" -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_CBSIZE 256 @@ -184,11 +165,5 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ - -#ifdef CONFIG_USE_IRQ -#error CONFIG_USE_IRQ not supported -#endif #endif