X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fsam9x60ek.h;h=27b39ebf41742df6a23ce9c584f22b6f3eae7bde;hb=2cc61a631bb8ae1acfadac9840abaa803091b7ac;hp=7716ac27fb90099922f82c82ee8b7a85a52f0dc9;hpb=fd690a5e932010d0309a859169aeb77af94dff24;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index 7716ac2..27b39eb 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -11,46 +11,28 @@
 #define __CONFIG_H__
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
+#define CFG_SYS_AT91_SLOW_CLOCK	32768
+#define CFG_SYS_AT91_MAIN_CLOCK	24000000	/* 24 MHz crystal */
 
 #define CONFIG_USART_BASE   ATMEL_BASE_DBGU
 #define CONFIG_USART_ID     0 /* ignored in arm */
 
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY            /* required until (g)pio is fixed */
-
 /*
  * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
  * NB: in this case, USB 1.1 devices won't be recognized.
  */
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE		0x20000000
-#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 megs */
-
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 + CONFIG_SYS_MALLOC_F_LEN - \
-	 GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_SDRAM_BASE		0x20000000
+#define CFG_SYS_SDRAM_SIZE		0x10000000	/* 256 megs */
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		0x40000000
-#define CONFIG_SYS_NAND_MASK_ALE	BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE	BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
-#endif
-
-#ifdef CONFIG_SD_BOOT
-/* bootstrap + u-boot + env + linux in sd card */
-
-#elif defined(CONFIG_NAND_BOOT)
-/* bootstrap + u-boot + env + linux in nandflash */
-
-#elif defined(CONFIG_QSPI_BOOT)
-/* bootstrap + u-boot + env + linux in SPI NOR flash */
+#define CFG_SYS_NAND_BASE		0x40000000
+#define CFG_SYS_NAND_MASK_ALE	BIT(21)
+#define CFG_SYS_NAND_MASK_CLE	BIT(22)
+#define CFG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
+#define CFG_SYS_NAND_READY_PIN	AT91_PIN_PD5
 #endif
 
 #endif