X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fpleb2.h;h=7dd6246f112f2b3cbf36ab91ac54c5c631d70461;hb=10d1a160f5e28b05f891c050ca2f23855b226f5f;hp=9e694118c5dae00864c02702b762f8c19bb4e546;hpb=6ca9da4d42aeb43df5ef29f7d0518009df583b2f;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 9e69411..7dd6246 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -39,24 +39,23 @@
 #undef CONFIG_LCD
 #undef CONFIG_MMC
 #define BOARD_LATE_INIT		1
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
 /* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
 
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
 
 /* None - PLEB 2 doesn't have any of this.
-	#define CONFIG_NET_MULTI
 	#define CONFIG_LAN91C96
 	#define CONFIG_LAN91C96_BASE 0x0C000000
  */
@@ -88,6 +87,7 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 
 
 #define CONFIG_BOOTDELAY	3
@@ -155,15 +155,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
@@ -179,6 +173,9 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
@@ -210,9 +207,9 @@
 #define CONFIG_SYS_GAFR2_U_VAL		0x00000000
 
 #define CONFIG_SYS_PSSR_VAL		0x20
-#define CONFIG_SYS_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CONFIG_SYS_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_CCCR		    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
+#define CONFIG_SYS_CKEN		    0x00000060	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
 
 /*
  * Memory settings
@@ -228,6 +225,9 @@
 					   /* bits set in lowlevel_init.S	*/
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */