X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fp1_p2_rdb_pc.h;h=c8d5e89338516dce716c5c75c08b62a19876f604;hb=a5d67547dd9c7a527dfda1967010e703a22441ff;hp=523af5265f6305f3e4d3335233e696c3c7c5d1bb;hpb=ec1eaad06551e2422baf8743f6987d4f561f2ce6;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 523af52..c8d5e89 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,9 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_P1020MBG) +#if defined(CONFIG_TARGET_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -21,19 +20,17 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020UTM) +#if defined(CONFIG_TARGET_P1020UTM) #define CONFIG_BOARDNAME "P1020UTM-PC" -#define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -58,10 +55,9 @@ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -83,10 +79,9 @@ "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif -#if defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1021 #define CONFIG_QE #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of @@ -118,10 +113,9 @@ #endif #endif -#if defined(CONFIG_P1024RDB) +#if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1024 #define CONFIG_SLIC #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 @@ -131,10 +125,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1025RDB) +#if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC @@ -148,10 +141,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PCA" +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P2020 #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -182,7 +174,6 @@ #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x20000 @@ -203,7 +194,6 @@ #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x20000 @@ -268,10 +258,6 @@ #endif #endif -/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 - #define CONFIG_MP #define CONFIG_FSL_ELBC @@ -282,7 +268,6 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -292,7 +277,7 @@ #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -306,8 +291,6 @@ #define CONFIG_L2_CACHE #define CONFIG_BTB -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ - #define CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT @@ -329,14 +312,13 @@ #endif /* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -347,11 +329,10 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_TARGET_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -406,10 +387,10 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_P1020UTM) +#elif defined(CONFIG_TARGET_P1020UTM) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #define CONFIG_SYS_FLASH_BASE 0xee000000 #else @@ -455,7 +436,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) @@ -466,7 +447,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ @@ -584,7 +565,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) @@ -755,7 +736,7 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* * QE UEC ethernet configuration */ @@ -789,7 +770,7 @@ #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 #endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_P1025RDB */ +#endif /* CONFIG_TARGET_P1025RDB */ /* * Environment @@ -853,12 +834,10 @@ #endif #endif -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR