X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fp1_p2_rdb_pc.h;h=92008cd38e49326041955ed009d714b0dd7ecc87;hb=83d4b7b1e7d785574bba43a66a3b35bdeb080833;hp=cb3dcc0c33af6375da354ad2453100b6b8c786a0;hpb=fc8d3b9a2f03eb6a92e1b34c6d841285a6d47bb1;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index cb3dcc0..92008cd 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -14,7 +14,6 @@
 
 #if defined(CONFIG_TARGET_P1020RDB_PC)
 #define CONFIG_BOARDNAME "P1020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK		0x03
@@ -41,7 +40,6 @@
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_BOARDNAME "P1020RDB-PD"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK		0x03
@@ -58,7 +56,6 @@
 
 #if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_BOARDNAME "P2020RDB-PC"
-#define CONFIG_NAND_FSL_ELBC
 #define CONFIG_VSC7385_ENET
 #define __SW_BOOT_MASK		0x03
 #define __SW_BOOT_NOR		0xc8
@@ -85,9 +82,7 @@
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
-#endif
-
-#ifdef CONFIG_SPIFLASH
+#elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
@@ -101,20 +96,16 @@
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SPL_COMMON_INIT_DDR
 #endif
-#endif
-
-#ifdef CONFIG_MTD_RAW_NAND
+#elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_NAND_INIT
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SPL_MAX_SIZE		(128 << 10)
-#define CONFIG_TPL_TEXT_BASE		0xf8f81000
 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(832 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000)
 #define CONFIG_SYS_NAND_U_BOOT_START	(0x11000000)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	((128 + 128) << 10)
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
@@ -123,7 +114,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(128 << 10)
 #define CONFIG_SYS_NAND_U_BOOT_DST	0xf8f80000
 #define CONFIG_SYS_NAND_U_BOOT_START	0xf8f80000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
 #endif /* not CONFIG_TPL_BUILD */
 
 #define CONFIG_SPL_PAD_TO		0x20000
@@ -137,7 +127,7 @@
 
 #ifndef CONFIG_SYS_MONITOR_BASE
 #ifdef CONFIG_TPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_TPL_TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE	0xf8f81000
 #elif defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
@@ -147,18 +137,9 @@
 
 #define CONFIG_PCIE1	/* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controller 2 (slot 2) */
-#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
 
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_LBA48
 
-#if defined(CONFIG_TARGET_P2020RDB)
-#define CONFIG_SYS_CLK_FREQ	100000000
-#else
-#define CONFIG_SYS_CLK_FREQ	66666666
-#endif
-#define CONFIG_DDR_CLK_FREQ	66666666
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -179,7 +160,6 @@
 
 /* DDR Setup */
 #define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
@@ -273,8 +253,6 @@
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
-
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
@@ -292,11 +270,6 @@
 
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
-#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-#else
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
-#endif
 
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
@@ -346,7 +319,6 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)/* Reserved for malloc */
 
 #define CONFIG_SYS_CPLD_BASE	0xffa00000
 #ifdef CONFIG_PHYS_64BIT
@@ -367,22 +339,6 @@
 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				 OR_GPCM_EAD)
 
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#else
-#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-#endif
-#define CONFIG_SYS_BR3_PRELIM	CONFIG_CPLD_BR_PRELIM	/* CPLD Base Address */
-#define CONFIG_SYS_OR3_PRELIM	CONFIG_CPLD_OR_PRELIM	/* CPLD Options */
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR			"vscfw_addr=ef000000"
@@ -400,9 +356,6 @@
 			OR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \
 			OR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)
 
-#define CONFIG_SYS_BR2_PRELIM	CONFIG_SYS_VSC7385_BR_PRELIM
-#define CONFIG_SYS_OR2_PRELIM	CONFIG_SYS_VSC7385_OR_PRELIM
-
 /* The size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE_SIZE	8192
 #endif
@@ -543,12 +496,6 @@
 #define CONFIG_HAS_ETH2
 #endif /* CONFIG_TSEC_ENET */
 
-#ifdef CONFIG_QE
-/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FW_ADDR	0xefec0000
-#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
-#endif /* CONFIG_QE */
-
 /*
  * Environment
  */
@@ -574,7 +521,6 @@
 #if defined(CONFIG_HAS_FSL_DR_USB)
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
 #endif
 #endif
 
@@ -586,12 +532,9 @@
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
-#undef CONFIG_WATCHDOG	/* watchdog disabled */
-
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
 
 /*
  * For booting Linux, the board info and command line data
@@ -601,10 +544,6 @@
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
 
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
 /*
  * Environment Configuration
  */
@@ -613,9 +552,6 @@
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
 
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR	1000000
-
 #ifdef __SW_BOOT_NOR
 #define __NOR_RST_CMD	\
 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
@@ -675,23 +611,6 @@ __stringify(__SD_RST_CMD)"\0" \
 __stringify(__NAND_RST_CMD)"\0" \
 __stringify(__PCIE_RST_CMD)"\0"
 
-#define CONFIG_NFSBOOTCOMMAND	\
-"setenv bootargs root=/dev/nfs rw "	\
-"nfsroot=$serverip:$rootpath "	\
-"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-"console=$consoledev,$baudrate $othbootargs;" \
-"tftp $loadaddr $bootfile;"	\
-"tftp $fdtaddr $fdtfile;"	\
-"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_HDBOOT	\
-"setenv bootargs root=/dev/$bdev rw rootdelay=30 "	\
-"console=$consoledev,$baudrate $othbootargs;" \
-"usb start;"	\
-"ext2load usb 0:1 $loadaddr /boot/$bootfile;"	\
-"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"	\
-"bootm $loadaddr - $fdtaddr"
-
 #define CONFIG_USB_FAT_BOOT	\
 "setenv bootargs root=/dev/ram rw "	\
 "console=$consoledev,$baudrate $othbootargs " \
@@ -717,15 +636,4 @@ __stringify(__PCIE_RST_CMD)"\0"
 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"	\
 "bootm $norbootaddr - $norfdtaddr"
 
-#define CONFIG_RAMBOOTCOMMAND	\
-"setenv bootargs root=/dev/ram rw "	\
-"console=$consoledev,$baudrate $othbootargs " \
-"ramdisk_size=$ramdisk_size;"	\
-"tftp $ramdiskaddr $ramdiskfile;"	\
-"tftp $loadaddr $bootfile;"	\
-"tftp $fdtaddr $fdtfile;"	\
-"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND	CONFIG_HDBOOT
-
 #endif /* __CONFIG_H */