X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fp1_p2_rdb_pc.h;h=5d0a570b6a2e45cc8722971431757a820ef83f1b;hb=bb6b142fc16713bb83e471912e614ac01eec4584;hp=9b5895093daa255193ee36f1dce1744aee9f09f2;hpb=25b4adbba018633b943a99322bfb2fb819c0bafb;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9b58950..5d0a570 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,13 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_DISPLAY_BOARDINFO -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - #if defined(CONFIG_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" #define CONFIG_P1020 @@ -41,7 +36,6 @@ #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 -#define CONFIG_SPI_FLASH #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -70,7 +64,6 @@ #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1020 -#define CONFIG_SPI_FLASH #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -80,6 +73,16 @@ #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#define MTDIDS_DEFAULT "nor0=ec000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ + "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif #if defined(CONFIG_P1021RDB) @@ -87,7 +90,6 @@ #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1021 #define CONFIG_QE -#define CONFIG_SPI_FLASH #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of addresses in the LBC */ @@ -98,6 +100,24 @@ #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c #define CONFIG_SYS_L2_SIZE (256 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9728k(fs)," \ + "256k(qe-ucode-firmware),1280k(u-boot)" +#endif #endif #if defined(CONFIG_P1024RDB) @@ -105,7 +125,6 @@ #define CONFIG_NAND_FSL_ELBC #define CONFIG_P1024 #define CONFIG_SLIC -#define CONFIG_SPI_FLASH #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 #define __SW_BOOT_SPI 0x08 @@ -120,7 +139,6 @@ #define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC -#define CONFIG_SPI_FLASH #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of addresses in the LBC */ @@ -136,7 +154,6 @@ #define CONFIG_BOARDNAME "P2020RDB-PCA" #define CONFIG_NAND_FSL_ELBC #define CONFIG_P2020 -#define CONFIG_SPI_FLASH #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -145,6 +162,22 @@ #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) +/* + * Dynamic MTD Partition support with mtdparts + */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_FLASH_CFI_MTD +#ifdef CONFIG_PHYS_64BIT +#define MTDIDS_DEFAULT "nor0=fef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#else +#define MTDIDS_DEFAULT "nor0=ef000000.nor" +#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ + "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" +#endif #endif #ifdef CONFIG_SDCARD @@ -269,8 +302,8 @@ #define CONFIG_FSL_ELBC #define CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ @@ -397,7 +430,6 @@ * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable */ - /* * Local Bus Definitions */ @@ -412,7 +444,6 @@ #define CONFIG_SYS_FLASH_BASE 0xef000000 #endif - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) #else @@ -450,7 +481,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #if defined(CONFIG_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) @@ -545,7 +575,6 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */ #define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */ - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define CONFIG_SYS_VSC7385_BASE 0xffb00000 @@ -613,7 +642,6 @@ */ #define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -627,20 +655,6 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* - * Pass open firmware flat tree - */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL @@ -665,7 +679,6 @@ /* enable read and write access to EEPROM */ #define CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_MULTI_EEPROMS #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -674,11 +687,8 @@ * eSPI - Enhanced SPI */ #define CONFIG_HARD_SPI -#define CONFIG_FSL_ESPI #if defined(CONFIG_SPI_FLASH) -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_MODE 0 #endif @@ -730,9 +740,7 @@ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ #define CONFIG_CMD_PCI -#define CONFIG_CMD_NET #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION @@ -855,15 +863,8 @@ /* * Command line configuration. */ -#include - #define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII #define CONFIG_CMD_DATE -#define CONFIG_CMD_ELF -#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_REGINFO /* @@ -875,7 +876,6 @@ #define CONFIG_USB_EHCI #ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #define CONFIG_USB_STORAGE @@ -891,14 +891,11 @@ #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC #endif #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ || defined(CONFIG_FSL_SATA) -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION #endif @@ -943,7 +940,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_BAUDRATE 115200 @@ -989,7 +985,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"fdtaddr=c00000\0" \ +"fdtaddr=1e00000\0" \ "bdev=sda1\0" \ "jffs2nor=mtdblock3\0" \ "norbootaddr=ef080000\0" \