X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fp1_p2_rdb_pc.h;h=07a75b9a1e77aae9d6c1c50a48b11b072a9e2b9d;hb=c88ecf47bdcd0af21b23a3317116bcd956f1e775;hp=276a693823f2c01974c52194631673eecf481ba4;hpb=3c594d34c4addc962b2bd6ed2d16f3ce24ab1627;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 276a693..07a75b9 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,9 +10,8 @@ #ifndef __CONFIG_H #define __CONFIG_H -#if defined(CONFIG_P1020MBG) +#if defined(CONFIG_TARGET_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -21,19 +20,17 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020UTM) +#if defined(CONFIG_TARGET_P1020UTM) #define CONFIG_BOARDNAME "P1020UTM-PC" -#define CONFIG_P1020 #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xe0 #define __SW_BOOT_SD 0x50 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1020RDB_PC) +#if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -58,10 +55,9 @@ * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_BOARDNAME "P1020RDB-PD" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1020 #define CONFIG_VSC7385_ENET #define CONFIG_SLIC #define __SW_BOOT_MASK 0x03 @@ -76,17 +72,12 @@ */ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=ec000000.nor" -#define MTDPARTS_DEFAULT "mtdparts=ec000000.nor:128k(dtb),6016k(kernel)," \ - "57088k(fs),1m(vsc7385-firmware),1280k(u-boot)" #endif -#if defined(CONFIG_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define CONFIG_BOARDNAME "P1021RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1021 #define CONFIG_QE #define CONFIG_VSC7385_ENET #define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of @@ -103,25 +94,12 @@ */ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS #define CONFIG_FLASH_CFI_MTD -#ifdef CONFIG_PHYS_64BIT -#define MTDIDS_DEFAULT "nor0=fef000000.nor" -#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ - "256k(dtb),4608k(kernel),9728k(fs)," \ - "256k(qe-ucode-firmware),1280k(u-boot)" -#else -#define MTDIDS_DEFAULT "nor0=ef000000.nor" -#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ - "256k(dtb),4608k(kernel),9728k(fs)," \ - "256k(qe-ucode-firmware),1280k(u-boot)" -#endif #endif -#if defined(CONFIG_P1024RDB) +#if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1024 #define CONFIG_SLIC #define __SW_BOOT_MASK 0xf3 #define __SW_BOOT_NOR 0x00 @@ -131,10 +109,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P1025RDB) +#if defined(CONFIG_TARGET_P1025RDB) #define CONFIG_BOARDNAME "P1025RDB" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P1025 #define CONFIG_QE #define CONFIG_SLIC @@ -148,10 +125,9 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PCA" +#if defined(CONFIG_TARGET_P2020RDB) +#define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -#define CONFIG_P2020 #define CONFIG_VSC7385_ENET #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 @@ -165,24 +141,13 @@ */ #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS #define CONFIG_FLASH_CFI_MTD -#ifdef CONFIG_PHYS_64BIT -#define MTDIDS_DEFAULT "nor0=fef000000.nor" -#define MTDPARTS_DEFAULT "mtdparts=fef000000.nor:256k(vsc7385-firmware)," \ - "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" -#else -#define MTDIDS_DEFAULT "nor0=ef000000.nor" -#define MTDPARTS_DEFAULT "mtdparts=ef000000.nor:256k(vsc7385-firmware)," \ - "256k(dtb),4608k(kernel),9984k(fs),1280k(u-boot)" -#endif #endif #ifdef CONFIG_SDCARD #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x20000 @@ -203,7 +168,6 @@ #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_PAD_TO 0x20000 @@ -268,14 +232,8 @@ #endif #endif -/* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 - #define CONFIG_MP -#define CONFIG_FSL_ELBC -#define CONFIG_PCI #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -283,17 +241,14 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CMD_SATA -#define CONFIG_SATA_SIL #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_LIBATA #define CONFIG_LBA48 -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SYS_CLK_FREQ 100000000 #else #define CONFIG_SYS_CLK_FREQ 66666666 @@ -307,8 +262,6 @@ #define CONFIG_L2_CACHE #define CONFIG_BTB -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ - #define CONFIG_ENABLE_36BIT_PHYS #ifdef CONFIG_PHYS_64BIT @@ -330,14 +283,13 @@ #endif /* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 #undef CONFIG_FSL_DDR_INTERACTIVE -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -348,11 +300,10 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Default settings for DDR3 */ -#ifndef CONFIG_P2020RDB +#ifndef CONFIG_TARGET_P2020RDB #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 @@ -407,10 +358,10 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_P1020MBG) || defined(CONFIG_P1020RDB_PD)) +#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_P1020UTM) +#elif defined(CONFIG_TARGET_P1020UTM) #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #define CONFIG_SYS_FLASH_BASE 0xee000000 #else @@ -455,8 +406,7 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #else #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) @@ -467,7 +417,7 @@ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \ | OR_FCM_PGS /* Large Page*/ \ | OR_FCM_CSCT \ @@ -585,7 +535,7 @@ #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024) #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024) -#if defined(CONFIG_P2020RDB) +#if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10) #else #define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10) @@ -652,7 +602,6 @@ #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -713,11 +662,7 @@ #endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_CMD_PCI - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -743,8 +688,6 @@ #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ - #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -757,7 +700,7 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_P1025RDB +#ifdef CONFIG_TARGET_P1025RDB /* * QE UEC ethernet configuration */ @@ -791,13 +734,12 @@ #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 #endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_P1025RDB */ +#endif /* CONFIG_TARGET_P1025RDB */ /* * Environment */ #ifdef CONFIG_SPIFLASH -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 10000000 @@ -806,7 +748,6 @@ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_SDCARD) -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 @@ -817,15 +758,12 @@ #else #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #endif -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET (1024 * 1024) #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) #elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) #define CONFIG_ENV_SIZE 0x2000 #else -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -835,41 +773,25 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * Command line configuration. - */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_REGINFO - -/* * USB */ #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_DESC_BIG_ENDIAN #endif #endif -#if defined(CONFIG_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_GENERIC_MMC -#endif - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ - || defined(CONFIG_FSL_SATA) -#define CONFIG_DOS_PARTITION #endif #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -880,15 +802,6 @@ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ /* * For booting Linux, the board info and command line data @@ -913,10 +826,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTARGS /* the boot command will set bootargs */ - -#define CONFIG_BAUDRATE 115200 - #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \