X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fot1200.h;h=776835a766e4c02efcd3cb04a59ed97e7231218f;hb=747fed56d3876d7de89959f9a927901e02166151;hp=8ca6f62850327c23e003ee3f945e986bf36dde29;hpb=7f513e8196589e3b1274132abe3b59e52979e3e5;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index 8ca6f62..776835a 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -1,8 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. * Copyright (C) 2014 Bachmann electronic GmbH - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -13,15 +12,11 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_MISC_INIT_R - /* UART Configs */ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE /* SF Configs */ -#define CONFIG_SPI -#define CONFIG_MXC_SPI #define CONFIG_SF_DEFAULT_BUS 2 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 25000000 @@ -31,8 +26,6 @@ #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO /* I2C Configs */ #define CONFIG_SYS_I2C @@ -61,23 +54,19 @@ * SATA Configs */ #ifdef CONFIG_CMD_SATA -#define CONFIG_DWC_AHSATA #define CONFIG_SYS_SATA_MAX_DEVICE 1 #define CONFIG_DWC_AHSATA_PORT_ID 0 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR #define CONFIG_LBA48 -#define CONFIG_LIBATA #endif /* SPL */ #ifdef CONFIG_SPL #include "imx6_spl.h" #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) -#define CONFIG_SPL_SPI_LOAD #endif #define CONFIG_FEC_MXC -#define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE MII100 #define CONFIG_ETHPRIME "FEC" @@ -97,11 +86,7 @@ /* Thermal support */ #define CONFIG_IMX_THERMAL -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM