X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fomapl138_lcdk.h;h=af0093511a02a53e38e0a956f38328981ccfd5b5;hb=dd11fdc31fb82f63258c1970a6d8d22b8ffd3173;hp=81ca68de9bcc8127e8c4ddbf7089587652d9a240;hpb=4e5909450ec2acafb3d2e5b9714251ae67e0f0e0;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 81ca68d..af00935 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -17,22 +17,22 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_OSCIN_FREQ		24000000
-#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
-#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
+#define CFG_SYS_OSCIN_FREQ		24000000
+#define CFG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
+#define CFG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 
 /*
  * Memory Info
  */
 #define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
 #define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
+#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 
 /* memtest start addr */
 
 /* memtest will be run on 16MB */
 
-#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+#define CFG_SYS_DA850_SYSCFG_SUSPSRC (	\
 	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
 	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
 	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
@@ -44,17 +44,17 @@
  */
 
 /* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */
-#define CONFIG_SYS_DA850_PLL0_PLLM     18
-#define CONFIG_SYS_DA850_PLL1_PLLM     21
+#define CFG_SYS_DA850_PLL0_PLLM     18
+#define CFG_SYS_DA850_PLL1_PLLM     21
 
 /*
  * DDR2 memory configuration
  */
-#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
+#define CFG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
 					DV_DDR_PHY_EXT_STRBEN | \
 					(0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDBCR (		  \
+#define CFG_SYS_DA850_DDR2_SDBCR (		  \
 	(1 << DV_DDR_SDCR_DDR2EN_SHIFT)		| \
 	(1 << DV_DDR_SDCR_DDREN_SHIFT)		| \
 	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT)	| \
@@ -64,9 +64,9 @@
 	(2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
 
 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
-#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
+#define CFG_SYS_DA850_DDR2_SDBCR2 0
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR (		  \
+#define CFG_SYS_DA850_DDR2_SDTIMR (		  \
 	(19 << DV_DDR_SDTMR1_RFC_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_RP_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_RCD_SHIFT)		| \
@@ -76,7 +76,7 @@
 	(1 << DV_DDR_SDTMR1_RRD_SHIFT)		| \
 	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		  \
+#define CFG_SYS_DA850_DDR2_SDTIMR2 (		  \
 	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT)	| \
 	(2 << DV_DDR_SDTMR2_XP_SHIFT)		| \
 	(0 << DV_DDR_SDTMR2_ODT_SHIFT)		| \
@@ -85,21 +85,21 @@
 	(1 << DV_DDR_SDTMR2_RTP_SHIFT)		| \
 	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
 
-#define CONFIG_SYS_DA850_DDR2_SDRCR    0x00000492
-#define CONFIG_SYS_DA850_DDR2_PBBPR    0x30
+#define CFG_SYS_DA850_DDR2_SDRCR    0x00000492
+#define CFG_SYS_DA850_DDR2_PBBPR    0x30
 
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
-#define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
+#define CFG_SYS_SPI_BASE		DAVINCI_SPI1_BASE
+#define CFG_SYS_SPI_CLK		clk_get(DAVINCI_SPI1_CLKID)
 
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_I2C_EXPANDER_ADDR	0x20
+#define CFG_SYS_I2C_EXPANDER_ADDR	0x20
 
 /*
  * Flash & Environment
@@ -109,7 +109,6 @@
 #define CFG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
 #define CFG_SYS_NAND_MASK_CLE	0x10
 #define CFG_SYS_NAND_MASK_ALE	0x8
-#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
 #define CFG_SYS_NAND_U_BOOT_SIZE	SZ_512K
 #define CFG_SYS_NAND_U_BOOT_DST	0xc1080000
 #define CFG_SYS_NAND_U_BOOT_START	CFG_SYS_NAND_U_BOOT_DST
@@ -138,7 +137,7 @@
 
 #include <environment/ti/mmc.h>
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#define CFG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	DEFAULT_MMC_TI_ARGS \
 	"bootpart=0:2\0" \
@@ -154,7 +153,7 @@
 /* defines for SPL */
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0xc0000000
+#define CFG_SYS_SDRAM_BASE		0xc0000000
 
 #include <asm/arch/hardware.h>