X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_sdp3430.h;h=2a890c9c7e8c81e24681974598cec1b8f554fbb2;hb=bb367b95f9204115bd6eac82e839b5590e6da4eb;hp=6a826ba69b671b95595b9bf325aae11a544f7d03;hpb=684cad5717ea5887a09f3c67732a17774a658b34;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 6a826ba..2a890c9 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -38,7 +38,6 @@
  */
 #define CONFIG_OMAP		1	/* in a TI OMAP core */
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
-#define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */
 
 #define CONFIG_SDRC	/* The chip has SDRC controller */
@@ -62,7 +61,6 @@
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
 
-#undef CONFIG_USE_IRQ			/* no support for IRQs */
 #define CONFIG_MISC_INIT_R
 
 #define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
@@ -138,9 +136,6 @@
 #define CONFIG_SYS_I2C_BUS_SELECT	1
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
-/* DDR - I use Infineon DDR */
-#define CONFIG_OMAP3_INFINEON_DDR	1
-
 /* OMITTED:  single 1 Gbit MT29F1G NAND flash */
 
 /*
@@ -201,7 +196,6 @@
  */
 #if defined(CONFIG_CMD_NET)
 
-#define CONFIG_NET_MULTI
 #define CONFIG_LAN91C96
 #define CONFIG_LAN91C96_BASE	DEBUG_BASE
 #define CONFIG_LAN91C96_EXT_PHY
@@ -268,7 +262,6 @@
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_SYS_PROMPT		"OMAP34XX SDP # "
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
@@ -299,17 +292,6 @@
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000
 
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128 << 10) /* Regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4 << 10) /* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4 << 10) /* FIQ stack */
-#endif
-
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
 #define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
 #define CONFIG_SYS_INIT_RAM_SIZE	0x800
@@ -324,9 +306,6 @@
 #define PHYS_SDRAM_1_SIZE	(32 << 20) /* at least 32 meg */
 #define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
 
-/* SDRAM Bank Allocation method */
-#define SDRC_R_B_C		1
-
 /*--------------------------------------------------------------------------*/
 
 /*
@@ -359,4 +338,6 @@
  *  - rest for filesystem
  */
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 #endif				/* __CONFIG_H */