X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_logic.h;h=05a43610e524c258e74467c0dd30c18b773903a9;hb=c6b968da78ce3fa7224c0ddf15fe170c7c05b27e;hp=0d03c75ce3012a28043154aa13d7df63e9ef1f31;hpb=1cad23c5f471d695bed1e3907e30caee3c2a3056;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 0d03c75..05a4361 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -11,146 +11,125 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* High Level Configuration Options */ + +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + /* - * High Level Configuration Options + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. */ -#define CONFIG_OMAP /* in a TI OMAP core */ -#define CONFIG_OMAP34XX /* which is a 34XX */ -#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SYS_TEXT_BASE 0x80400000 +#include -#define CONFIG_SDRC /* The chip has SDRC controller */ +/* Override default SPL info to minimize empty space and allow BCH8 in SPL */ +#undef CONFIG_SPL_TEXT_BASE +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_TEXT_BASE 0x40200000 +#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE) -#include /* get chip and board defs */ -#include +/* Display CPU and Board information */ -/* - * Display CPU and Board information - */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */ -#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */ - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ +/* Hardware drivers */ -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_USB_OMAP3 -/* - * select serial console configuration - */ +/* select serial console configuration */ +#undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 #define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */ -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_OMAP_HSMMC -#define CONFIG_DOS_PARTITION - /* commands to include */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=omap2-nand.0" -#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\ - "1920k(u-boot),128k(u-boot-env),"\ - "4m(kernel),-(fs)" - -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SETEXPR /* Evaluate expressions */ - -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ -#define CONFIG_SYS_NO_FLASH - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +/* I2C */ #define CONFIG_SYS_I2C_OMAP34XX - -/* - * TWL4030 - */ -#define CONFIG_TWL4030_POWER - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_QUIET_TEST +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ +#define EXPANSION_EEPROM_I2C_BUS 2 /* I2C Bus for AT24C64 */ +#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID + +/* USB */ +#define CONFIG_USB_MUSB_OMAP2PLUS +#define CONFIG_USB_MUSB_PIO_ONLY +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETHER_RNDIS +#define CONFIG_USB_FUNCTION_FASTBOOT +#define CONFIG_CMD_FASTBOOT +#define CONFIG_ANDROID_BOOT_IMAGE +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 + +/* TWL4030 */ +#define CONFIG_TWL4030_PWM +#define CONFIG_TWL4030_USB + +/* Board NAND Info. */ +#ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ + +#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */ +#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */ +#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */ +#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */ + +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ + 13, 14, 16, 17, 18, 19, 20, 21, 22, \ + 23, 24, 25, 26, 27, 28, 30, 31, 32, \ + 33, 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 44, 45, 46, 47, 48, 49, 50, 51, \ + 52, 53, 54, 55, 56} + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 13 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW +#define CONFIG_BCH +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_MAX_ECCPOS 56 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" +#endif /* Environment information */ -#define CONFIG_BOOTDELAY 2 /* * PREBOOT assumes the 4.3" display is attached. User can interrupt @@ -159,7 +138,7 @@ #define CONFIG_PREBOOT \ "echo ======================NOTICE============================;"\ "echo \"The u-boot environment is not set.\";" \ - "echo \"If using a display a valid display varible for your panel\";" \ + "echo \"If using a display a valid display variable for your panel\";" \ "echo \"needs to be set.\";" \ "echo \"Valid display options are:\";" \ "echo \" 2 == LQ121S1DG31 TFT SVGA (12.1) Sharp\";" \ @@ -174,15 +153,20 @@ "echo \"Defaulting to 4.3 LCD panel (display=15).\";" \ "setenv display 15;" \ "setenv preboot;" \ + "nand unlock;" \ "saveenv;" - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ - "bootfile=uImage\0" \ + "uimage=uImage\0" \ + "zimage=zImage\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ + "nandrootfstype=ubifs rootwait\0" \ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ @@ -200,133 +184,115 @@ "setenv bootargs ${bootargs} omapfb.vrfb=y " \ "omapfb.rotate=${rotation}; " \ "fi\0" \ - "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \ + "optargs=ignore_loglevel early_printk no_console_suspend\0" \ "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \ "common_bootargs=setenv bootargs ${bootargs} display=${display} " \ - "${otherbootargs};" \ + "${optargs};" \ "run addmtdparts; " \ "run vrfb_arg\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo 'Running bootscript from mmc ...'; " \ "source ${loadaddr}\0" \ - "loaduimage=mmc rescan ${mmcdev}; " \ - "fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \ + "loadzimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \ "ramdisksize=64000\0" \ "ramdiskaddr=0x82000000\0" \ "ramdiskimage=rootfs.ext2.gz.uboot\0" \ + "loadramdisk=mmc rescan; " \ + "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \ "ramargs=run setconsole; setenv bootargs console=${console} " \ "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ - "mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \ + "mmcargs=run setconsole; setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "nandargs=run setconsole; setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "fdtaddr=0x86000000\0" \ + "loadfdtimage=mmc rescan; " \ + "fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ + "mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \ + "run mmcargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loadzimage; " \ + "run loadfdtimage; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \ "run ramargs; " \ "run common_bootargs; " \ "run dump_bootargs; " \ "run loaduimage; " \ - "fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\ + "run loadramdisk; " \ "bootm ${loadaddr} ${ramdiskaddr}\0" \ - "ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ + "mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \ + "run ramargs; " \ + "run common_bootargs; " \ + "run dump_bootargs; " \ + "run loadzimage; " \ + "run loadramdisk; " \ + "run loadfdtimage; " \ + "bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \ + "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ "run ramargs; " \ "run common_bootargs; " \ "run dump_bootargs; " \ - "tftpboot ${loadaddr} ${bootfile}; "\ - "tftpboot ${ramdiskaddr} ${ramdiskimage}; "\ + "tftpboot ${loadaddr} ${uimage}; " \ + "tftpboot ${ramdiskaddr} ${ramdiskimage}; " \ "bootm ${loadaddr} ${ramdiskaddr}\0" #define CONFIG_BOOTCOMMAND \ "run autoboot" +/* Miscellaneous configurable options */ #define CONFIG_AUTO_COMPLETE -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "OMAP Logic # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + /* memtest works on */ #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ +/* FLASH and environment organization */ /* **** PISMO SUPPORT *** */ - -/* Configure the PISMO */ -#define PISMO1_NAND_SIZE GPMC_SIZE_128M - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#define CONFIG_SYS_FLASH_BASE NAND_BASE #elif defined(CONFIG_CMD_ONENAND) -#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE +#define CONFIG_SYS_FLASH_BASE ONENAND_MAP #endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_OMAP_GPMC -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET -#endif - #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -/* - * SMSC922x Ethernet - */ +/* SMSC922x Ethernet */ #if defined(CONFIG_CMD_NET) - #define CONFIG_SMC911X -#define CONFIG_SMC911X_16_BIT +#define CONFIG_SMC911X_32_BIT #define CONFIG_SMC911X_BASE 0x08000000 - #endif /* (CONFIG_CMD_NET) */ -/* - * BOOTP fields - */ +/* Defines for SPL */ -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#define CONFIG_SPL_OMAP3_ID_NAND + +/* NAND: SPL falcon mode configs */ +#ifdef CONFIG_SPL_OS_BOOT +#define CONFIG_CMD_SPL_NAND_OFS 0x240000 +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000 +#endif #endif /* __CONFIG_H */