X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap2420h4.h;h=47437b09c645f0e8f25d99dc6fb219a362f91ae2;hb=d0b0dcaa220549999d6ea74cf87487846c186a0f;hp=b933c249881469cc95fbafe30af66e319d5ad753;hpb=8ed9604613398660f9ee855060661da8809d4045;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index b933c24..47437b0 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -35,14 +35,20 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP2420 1 /* which is in a 2420 */ #define CONFIG_OMAP2420H4 1 /* and on a H4 board */ -//#define CONFIG_APTIX 1 /* define if on APTIX test chip */ -//#define CONFIG_VIRTIO 1 /* Using Virtio simulator */ +/*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ +/*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ -#define PRCM_CONFIG_II 1 -#define CONFIG_PARTIAL_SRAM 1 +/* Clock config to target*/ +#define PRCM_CONFIG_II 1 +/* #define PRCM_CONFIG_III 1 */ #include /* get chip and board defs */ +/* On H4, NOR and NAND flash are mutual exclusive. + Define this if you want to use NAND + */ +/*#define CONFIG_SYS_NAND_BOOT */ + #ifdef CONFIG_APTIX #define V_SCLK 1500000 #else @@ -59,22 +65,24 @@ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 /* * Size of malloc() pool */ -#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * Hardware drivers */ - + /* * SMC91c96 Etherent */ -#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_NET_MULTI +#define CONFIG_LAN91C96 #define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) #define CONFIG_LAN91C96_EXT_PHY @@ -87,11 +95,11 @@ #define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */ #endif -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE (-4) -#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ -#define CFG_NS16550_COM1 OMAP2420_UART1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */ +#define CONFIG_SYS_NS16550_COM1 OMAP2420_UART1 /* * select serial console configuration @@ -102,25 +110,43 @@ * I2C configuration */ #define CONFIG_HARD_I2C -#define CFG_I2C_SPEED 100000 -#define CFG_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_DRIVER_OMAP24XX_I2C /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C) -// I'd like to get to these. Snap kernel loads if we make MMC go // - // #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) +/* + * Command line configuration. + */ +#include -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#ifdef CONFIG_SYS_NAND_BOOT + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_I2C + #define CONFIG_CMD_NAND + #define CONFIG_CMD_JFFS2 +#else + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_I2C + #define CONFIG_CMD_JFFS2 -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + #undef CONFIG_CMD_SOURCE +#endif + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTDELAY 3 @@ -138,39 +164,35 @@ /* * Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ #ifdef CONFIG_APTIX -#define V_PROMPT "OMAP2420 Aptix # " +# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " #else -#define V_PROMPT "OMAP242x H4 # " +# define CONFIG_SYS_PROMPT "OMAP242x H4 # " #endif - -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT V_PROMPT -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ -#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) -#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #ifdef CONFIG_APTIX -#define V_PVT 3 +#define V_PTV 3 #else -#define V_PVT 7 /* use with 12MHz/128 */ +#define V_PTV 7 /* use with 12MHz/128 */ #endif -#define CFG_TIMERBASE OMAP2420_GPT2 -#define CFG_PVT V_PVT /* 2^(pvt+1) */ -#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT)) +#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 +#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Stack sizes @@ -191,23 +213,61 @@ #define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP2420_SDRC_CS1 +#define PHYS_FLASH_SECT_SIZE SZ_128K #define PHYS_FLASH_1 H4_CS0_BASE /* Flash Bank #1 */ #define PHYS_FLASH_SIZE_1 SZ_32M #define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ #define PHYS_FLASH_SIZE_2 SZ_32M -#define CFG_FLASH_BASE PHYS_FLASH_1 /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_LEN SZ_128K /* Reserve 1 sector */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 } + +#ifdef CONFIG_SYS_NAND_BOOT +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE +#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ +#endif -#define CFG_ENV_ADDR (CFG_FLASH_BASE + SZ_128K) -#define CFG_ENV_IS_IN_FLASH 1 +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (10*75*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (10*75*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +#define CONFIG_SYS_JFFS2_MEM_NAND + +/* + * JFFS2 partitions + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_JFFS2_DEV "nor1" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor1=omap2420-1" +#define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" +*/ #endif /* __CONFIG_H */