X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap2420h4.h;h=12252ac129e096251d9013e02ea890f5d22852a5;hb=f8edca2e9a128f526b1fe6f997f7adb852cf5b3c;hp=85160546a7f210e84c97a50b0a6b57b3118c1eab;hpb=289f932c5ff628bf21a05073243071a01a2d3b02;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 8516054..12252ac 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -39,18 +39,15 @@
 /*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
 
 /* Clock config to target*/
-#define PRCM_CONFIG_II		1
-//#define PRCM_CONFIG_III	1
-
-/* Memory configuration on board */
-//#define CONFIG_OPTIMIZE_DDR	1
+#define PRCM_CONFIG_II	1
+/* #define PRCM_CONFIG_III		1 */
 
 #include <asm/arch/omap2420.h>        /* get chip and board defs */
 
 /* On H4, NOR and NAND flash are mutual exclusive.
    Define this if you want to use NAND
  */
-//#define CFG_NAND_BOOT
+/*#define CFG_NAND_BOOT */
 
 #ifdef CONFIG_APTIX
 #define V_SCLK                   1500000
@@ -125,11 +122,8 @@
 #ifdef CFG_NAND_BOOT
 #define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2)
 #else
-#define CONFIG_COMMANDS          (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2)
+#define CONFIG_COMMANDS          ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT)
 #endif
-/* I'd like to get to these. Snap kernel loads if we make MMC go */
-  /* #define CONFIG_COMMANDS       (CONFIG_CMD_DFL | CFG_CMD_NAND | CFG_CMD_JFFS2 | CFG_CMD_DHCP | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_I2C) */
-
 #define CONFIG_BOOTP_MASK        CONFIG_BOOTP_DEFAULT
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@@ -163,7 +157,6 @@
 #define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
 #define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
 
-
 #define NAND_CTL_CLRALE(nandptr)
 #define NAND_CTL_SETALE(nandptr)
 #define NAND_CTL_CLRCLE(nandptr)
@@ -171,7 +164,6 @@
 #define NAND_DISABLE_CE(nand)
 #define NAND_ENABLE_CE(nand)
 
-
 #define CONFIG_BOOTDELAY         3
 
 #ifdef NFS_BOOT_DEFAULTS
@@ -241,17 +233,21 @@
 #define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
 #define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
 
+#define PHYS_FLASH_SECT_SIZE     SZ_128K
 #define PHYS_FLASH_1             H4_CS0_BASE	   /* Flash Bank #1 */
 #define PHYS_FLASH_SIZE_1        SZ_32M
 #define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
 #define PHYS_FLASH_SIZE_2        SZ_32M
-#define CFG_FLASH_BASE           PHYS_FLASH_1
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
+#define CFG_FLASH_BASE           PHYS_FLASH_1
 #define CFG_MAX_FLASH_BANKS      2           /* max number of memory banks */
 #define CFG_MAX_FLASH_SECT       (259)	     /* max number of sectors on one chip */
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE /* Monitor at beginning of flash */
+#define CFG_MONITOR_LEN		SZ_128K      /* Reserve 1 sector */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLASH_BASE + PHYS_FLASH_SIZE_1 }
 
 #ifdef CFG_NAND_BOOT
 #define CFG_ENV_IS_IN_NAND	1
@@ -259,16 +255,39 @@
 #else
 #define CFG_ENV_ADDR             (CFG_FLASH_BASE + SZ_128K)
 #define	CFG_ENV_IS_IN_FLASH      1
+#define CFG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_OFFSET	( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */
 #endif
 
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI		1	/* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER	1	/* Use drivers/cfi_flash.c */
+#define CFG_FLASH_USE_BUFFER_WRITE 1	/* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION	1	/* Use hardware sector protection */
+
 /* timeout values are in ticks */
-#define CFG_FLASH_ERASE_TOUT     (30*75*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT     (30*75*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT     (100*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT     (100*CFG_HZ) /* Timeout for Flash Write */
 
-/* Flash banks JFFS2 should use */
-#define CFG_MAX_MTD_BANKS	(CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
 #define CFG_JFFS2_MEM_NAND
-#define CFG_JFFS2_FIRST_BANK	1		/* use flash_info[1] */
-#define CFG_JFFS2_NUM_BANKS     1
+
+/*
+ * JFFS2 partitions
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor1"
+#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET	0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nor1=omap2420-1"
+#define MTDPARTS_DEFAULT	"mtdparts=omap2420-1:-(jffs2)"
+*/
 
 #endif							/* __CONFIG_H */