X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmxs.h;h=fc15ed82c6ed1ad18eb4be8719c451b273b1f7f3;hb=a29491ade0adf3dbb9dc51be8b45530edde1f1df;hp=4bb3621a42860d6112dd0f5ce9e86849608e27e4;hpb=10d3e90f46feace58f4141b696d91644e594e3ed;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 4bb3621..fc15ed8 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -43,16 +43,7 @@
 
 /* Startup hooks */
 
-/* SPL */
-#ifndef CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH	"arch/arm/cpu/arm926ejs/mxs"
-#endif
-
 /* Memory sizes */
-#define CONFIG_SYS_MALLOC_LEN		0x00400000	/* 4 MB for malloc */
-#define CONFIG_SYS_MEMTEST_START	0x40000000	/* Memtest start adr */
-#define CONFIG_SYS_MEMTEST_END		0x40400000	/* 4 MB RAM test */
 
 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x00000000
@@ -63,10 +54,6 @@
 #endif
 
 /* Point initial SP in SRAM so SPL can use it too. */
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /*
  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
@@ -80,27 +67,12 @@
  * As for the SPL, we must avoid the first 4 KiB as well, but we load the
  * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB.
  */
-#define CONFIG_SPL_TEXT_BASE		0x00001000
 
 /* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
-#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-						/* Boot argument buffer size */
-
-/* Booting Linux */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
 
 /*
  * Drivers
  */
-
-/* APBH DMA */
-
-/* GPIO */
-#define CONFIG_MXS_GPIO
-
 /*
  * DUART Serial Driver.
  * Conflicts with AUART driver which can be set by board.
@@ -109,31 +81,10 @@
 #define CONFIG_PL01x_PORTS		{ (void *)MXS_UARTDBG_BASE }
 /* Default baudrate can be overridden by board! */
 
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_FEC_MXC
-#ifndef CONFIG_ETHPRIME
-#define CONFIG_ETHPRIME			"FEC0"
-#endif
-#ifndef CONFIG_FEC_XCV_TYPE
-#define CONFIG_FEC_XCV_TYPE		RMII
-#endif
-#endif
-
-/* LCD */
-#ifdef CONFIG_VIDEO
-#define CONFIG_VIDEO_MXS
-#endif
-
-/* MMC */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_BOUNCE_BUFFER
-#endif
-
 /* NAND */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0x60000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #endif
 
 /* OCOTP */
@@ -146,10 +97,4 @@
 #define CONFIG_SPI_HALF_DUPLEX
 #endif
 
-/* USB */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MXS
-#define CONFIG_EHCI_IS_TDI
-#endif
-
 #endif	/* __CONFIGS_MXS_H__ */