X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx7ulp_evk.h;h=b8dcaa10361d6df826941db4df778e9fe1550519;hb=d01806a8fcbdaedcc67cead56ece572021d97ab7;hp=31b6d3e448e83c93c654086d87ae1428532fce66;hpb=0bb430c8494e26e8d258cf6957cdd39d2ce4f309;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index 31b6d3e..b8dcaa1 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
  *
  * Configuration settings for the Freescale i.MX7ULP EVK board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __MX7ULP_EVK_CONFIG_H
@@ -28,8 +27,6 @@
 #define IRAM_BASE_ADDR			OCRAM_0_BASE
 #define IOMUXC_BASE_ADDR		IOMUXC1_RBASE
 
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 
@@ -47,7 +44,6 @@
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR			WDG1_RBASE
 
-#define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK		1000000 /* Fixed at 1Mhz from TSTMR */
 
 #define CONFIG_INITRD_TAG
@@ -65,7 +61,6 @@
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
 
 #define CONFIG_SYS_CACHELINE_SIZE      64
@@ -77,7 +72,6 @@
 #define CONFIG_SYS_MAXARGS		256
 
 /* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS		1
 
 #define PHYS_SDRAM			0x60000000
 #define PHYS_SDRAM_SIZE			SZ_1G
@@ -86,7 +80,6 @@
 
 #define CONFIG_LOADADDR             0x60800000
 
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_END      0x9E000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS \