X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx6ullevk.h;h=10d0969ac325b3d5cd7427d837807f77b35c42eb;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=b8eddf1da62aa53bb2f3027010e02caa2e3d0231;hpb=3788b451e32bc925c4a63a882acc9c3b4ee895be;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index b8eddf1..10d0969 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -1,9 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __MX6ULLEVK_CONFIG_H #define __MX6ULLEVK_CONFIG_H @@ -12,7 +11,7 @@ #include #include #include "mx6_common.h" -#include +#include #ifdef CONFIG_SECURE_BOOT #ifndef CONFIG_CSF_SIZE @@ -22,15 +21,9 @@ #define PHYS_SDRAM_SIZE SZ_512M -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) -#define CONFIG_BOARD_EARLY_INIT_F - -#define CONFIG_MXC_GPIO - #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE @@ -139,8 +132,6 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 -#define CONFIG_STACKSIZE SZ_128K - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -154,23 +145,28 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH - +/* environment organization */ #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_OFFSET (12 * SZ_64K) -#define CONFIG_CMD_BMODE - #define CONFIG_IMX_THERMAL #define CONFIG_IOMUX_LPSR #define CONFIG_SOFT_SPI +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_QSPI_FLASH_NUM 1 +#define FSL_QSPI_FLASH_SIZE SZ_32M +#endif + #endif