X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx31pdk.h;h=4765764f83a9edebf8e38ef9d26e9aeffc81fcb9;hb=87f78478a4a1bf574db0b0e575ca37cf91fb187c;hp=1282a6e77e3c244ade82dab0ab18a9244c37516b;hpb=e6f4042a04195be258f79e33abe3b71af9162862;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 1282a6e..4765764 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2008 Magnus Lilja * @@ -7,8 +8,6 @@ * Kshitij Gupta * * Configuration settings for the Freescale i.MX31 PDK board. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -17,13 +16,6 @@ #include /* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ - -#define CONFIG_SYS_GENERIC_BOARD - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -31,13 +23,9 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 2048 -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_TEXT_BASE 0x87dc0000 -#define CONFIG_SYS_TEXT_BASE 0x87e00000 #ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT @@ -54,10 +42,7 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_MXC_GPIO -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) @@ -74,32 +59,6 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#include - -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NAND -#define CONFIG_CMD_BOOTZ - -/* - * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require - * that CFG_NO_FLASH is undefined). - */ -#undef CONFIG_CMD_IMLS - -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_BOOTDELAY 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ @@ -112,19 +71,9 @@ "nand erase 0x0 0x40000; " \ "nand write 0x81000000 0x0 0x40000\0" -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0xB6000000 -#define CONFIG_SMC911X_32_BIT - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START 0x80000000 @@ -133,15 +82,11 @@ /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_CMDLINE_EDITING - /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR @@ -151,13 +96,9 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE) -/*----------------------------------------------------------------------- - * FLASH and environment organization +/* + * environment organization */ -/* No NOR flash present */ -#define CONFIG_SYS_NO_FLASH - -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x40000 #define CONFIG_ENV_OFFSET_REDUND 0x60000 #define CONFIG_ENV_SIZE (128 * 1024) @@ -165,7 +106,6 @@ /* * NAND driver */ -#define CONFIG_NAND_MXC #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR @@ -174,7 +114,7 @@ /* NAND configuration for the NAND_SPL */ -/* Start copying real U-boot from the second page */ +/* Start copying real U-Boot from the second page */ #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 /* Load U-Boot to this address */ @@ -187,7 +127,6 @@ #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - /* Configuration of lowlevel_init.S (clocks and SDRAM) */ #define CCM_CCMR_SETUP 0x074B0BF5 #define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \