X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx31pdk.h;h=3b86c9ebf356562f401c7c22efe38bc7fd850d5a;hb=178d0cc1a4c73c3341afbeb2a93b172de8c96bd1;hp=17d3143eba827943c9d88f1d99f10767b1c7382d;hpb=a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 17d3143..3b86c9e 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -35,8 +35,6 @@
 /* High Level Configuration Options */
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
-#define CONFIG_MX31_HCLK_FREQ	26000000
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -71,9 +69,9 @@
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 
 /* PMIC Controller */
-#define CONFIG_PMIC
-#define CONFIG_PMIC_SPI
-#define CONFIG_PMIC_FSL
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS	1
 #define CONFIG_FSL_PMIC_CS	2
 #define CONFIG_FSL_PMIC_CLK	1000000
@@ -205,11 +203,11 @@
 
 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 #define CCM_CCMR_SETUP		0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
-				 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
-				 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
-				 PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
+#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
+				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
+				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
 				 PLL_MFN(12))
 
 #define ESDMISC_MDDR_SETUP	0x00000004