X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx1fs2.h;h=90a8d8405b503fec999f866b1086f4aface3516a;hb=d1475d8aab7a6ab7ea7534a98bd20e59f150c2e3;hp=9816be8dc4fa10d76944ae709f7feb8dc58cf187;hpb=700a0c648df72f2c8e0589c0d0470b5ffd7cab7b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 9816be8..90a8d84 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -34,22 +34,30 @@ #undef _CONFIG_UART4 /* internal uart 4 */ #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ + /* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. + * BOOTP options */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - & ~CFG_CMD_NET \ - & ~CFG_CMD_PING \ - & ~CFG_CMD_DHCP \ - | CFG_CMD_JFFS2 \ - ) - -#include +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 + +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_SOURCE + /* * Boot options. Setting delay to -1 stops autostart count down. @@ -62,22 +70,20 @@ /* * General options for u-boot. Modify to save memory foot print */ -#define CFG_LONGHELP /* undef saves memory */ -#define CFG_PROMPT "mx1fs2> " /* prompt string */ -#define CFG_CBSIZE 256 /* console I/O buffer */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ -#define CFG_MAXARGS 16 /* max command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ - -#define CFG_MEMTEST_START 0x08100000 /* memtest test area */ -#define CFG_MEMTEST_END 0x08F00000 +#define CONFIG_SYS_LONGHELP /* undef saves memory */ +#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */ +#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */ +#define CONFIG_SYS_MAXARGS 16 /* max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */ -#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ +#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */ +#define CONFIG_SYS_MEMTEST_END 0x08F00000 -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x141 /* core clock - register value */ +#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_BAUDRATE 115200 /* * Definitions related to passing arguments to kernel. @@ -90,10 +96,10 @@ /* * Malloc pool need to host env + 128 Kb reserve for other allocations. */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) ) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CONFIG_STACKSIZE (120<<10) /* stack size */ @@ -127,8 +133,8 @@ * Flash Controller settings */ -#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ -#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ #ifdef BUS32BIT_VERSION #define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */ @@ -148,19 +154,19 @@ is not so clear to me. In other words we can provide more informations to user, but this expects more complex flash handling we do not provide now.*/ -#undef CFG_FLASH_CFI +#undef CONFIG_SYS_FLASH_CFI -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */ -#define CFG_FLASH_BASE MX1FS2_FLASH_BASE +#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE /* * This is setting for JFFS2 support in u-boot. * Right now there is no gain for user, but later on booting kernel might be * possible. Consider using XIP kernel running from flash to save RAM * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ /* @@ -168,7 +174,7 @@ */ /* No command line, one static partition, whole device */ /* -#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nor0" #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF #define CONFIG_JFFS2_PART_OFFSET 0x00050000 @@ -176,7 +182,9 @@ /* mtdparts command line support */ /* Note: fake mtd_id used, no linux mtd map file */ -#define CONFIG_JFFS2_CMDLINE +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=mx1fs2-0" #ifdef BUS32BIT_VERSION @@ -197,16 +205,16 @@ * env. has no sense to us. */ -#define CFG_MONITOR_BASE 0x10000000 -#define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ -#define CFG_ENV_SIZE 0x20000 +#define CONFIG_SYS_MONITOR_BASE 0x10000000 +#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */ +#define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ /* Setup CS4 and CS5 */ -#define CFG_GIUS_A_VAL 0x0003fffe +#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe /* * CSxU_VAL: @@ -218,14 +226,14 @@ * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| */ -#define CFG_CS0U_VAL 0x00008C00 -#define CFG_CS0L_VAL 0x22222601 -#define CFG_CS1U_VAL 0x00008C00 -#define CFG_CS1L_VAL 0x22222301 -#define CFG_CS4U_VAL 0x00008C00 -#define CFG_CS4L_VAL 0x22222301 -#define CFG_CS5U_VAL 0x00008C00 -#define CFG_CS5L_VAL 0x22222301 +#define CONFIG_SYS_CS0U_VAL 0x00008C00 +#define CONFIG_SYS_CS0L_VAL 0x22222601 +#define CONFIG_SYS_CS1U_VAL 0x00008C00 +#define CONFIG_SYS_CS1L_VAL 0x22222301 +#define CONFIG_SYS_CS4U_VAL 0x00008C00 +#define CONFIG_SYS_CS4L_VAL 0x22222301 +#define CONFIG_SYS_CS5U_VAL 0x00008C00 +#define CONFIG_SYS_CS5L_VAL 0x22222301 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) f_ref=16,777MHz @@ -244,25 +252,25 @@ 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ -#define CFG_MPCTL0_VAL 0x07E723AD -#define CFG_MPCTL1_VAL 0x00000040 -#define CFG_PCDR_VAL 0x00010005 -#define CFG_GPCR_VAL 0x00000FFB +#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD +#define CONFIG_SYS_MPCTL1_VAL 0x00000040 +#define CONFIG_SYS_PCDR_VAL 0x00010005 +#define CONFIG_SYS_GPCR_VAL 0x00000FFB #define USE_16M_OSZI /* If you have one, you want to use it The internal 32kHz oszillator jitters */ #ifdef USE_16M_OSZI -#define CFG_SPCTL0_VAL 0x04001401 -#define CFG_SPCTL1_VAL 0x0C000040 -#define CFG_CSCR_VAL 0x07030003 +#define CONFIG_SYS_SPCTL0_VAL 0x04001401 +#define CONFIG_SYS_SPCTL1_VAL 0x0C000040 +#define CONFIG_SYS_CSCR_VAL 0x07030003 #define CONFIG_SYS_CLK_FREQ 16780000 #define CONFIG_SYSPLL_CLK_FREQ 16000000 #else -#define CFG_SPCTL0_VAL 0x07E716D1 -#define CFG_CSCR_VAL 0x06000003 +#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1 +#define CONFIG_SYS_CSCR_VAL 0x06000003 #define CONFIG_SYS_CLK_FREQ 16780000 #define CONFIG_SYSPLL_CLK_FREQ 16780000 @@ -273,9 +281,9 @@ * one may expect. For instance loadb command do not cares :-) * So advice is - do not relay on this... */ -#define CFG_LOAD_ADDR 0x08400000 +#define CONFIG_SYS_LOAD_ADDR 0x08400000 -#define CFG_FMCR_VAL 0x00000003 /* Reset Default */ +#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */ /* Bit[0:3] contain PERCLK1DIV for UART 1 0x000b00b ->b<- -> 192MHz/12=16MHz @@ -283,20 +291,21 @@ 0x000b00b ->3<- -> 64MHz/4=16MHz */ #ifdef _CONFIG_UART1 +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL1 #elif defined _CONFIG_UART2 +#define CONFIG_IMX_SERIAL #define CONFIG_IMX_SERIAL2 #elif defined _CONFIG_UART3 | defined _CONFIG_UART4 -#define CONFIG_IMX_SERIAL_NONE -#define CFG_NS16550 -#define CFG_NS16550_SERIAL -#define CFG_NS16550_CLK 3686400 -#define CFG_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK 3686400 +#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_CONS_INDEX 1 #ifdef _CONFIG_UART3 -#define CFG_NS16550_COM1 0x15000000 +#define CONFIG_SYS_NS16550_COM1 0x15000000 #elif defined _CONFIG_UART4 -#define CFG_NS16550_COM1 0x16000000 +#define CONFIG_SYS_NS16550_COM1 0x16000000 #endif #endif