X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmucmc52.h;h=101788a678580b99d9297f464ce6a4227b580091;hb=3d6ba91e793808d1612152e9f9b8c51b3ca6c926;hp=8971f0b6c8df546f0dc3617e166c3140e35f71bc;hpb=225f0eaa745adfae05931848543d99942798756a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index 8971f0b..101788a 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * (C) Copyright 2003-2005 @@ -32,319 +32,85 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_HOSTNAME mucmc52 -#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 #endif -#define CONFIG_BOARD_EARLY_INIT_R +#include "manroland/common.h" +#include "manroland/mpc5200-common.h" #define CONFIG_LAST_STAGE_INIT - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } -/* Partitions */ -#define CONFIG_DOS_PARTITION - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DTT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CFG_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CFG_I2C_SPEED 100000 /* 100 kHz */ -#define CFG_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -/* for LM81 */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CFG_DTT_MAX_TEMP 70 -#define CFG_DTT_LOW_TEMP -30 -#define CFG_DTT_HYSTERESIS 3 /* * Flash configuration */ -#define CFG_FLASH_BASE 0xFF800000 - -#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CFG_FLASH_CFI -#define CFG_FLASH_EMPTY_INFO -#define CFG_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* * Environment settings */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 -#define CFG_DISPLAY_BASE 0x80600000 -#define CFG_STATUS1_BASE 0x80600200 -#define CFG_STATUS2_BASE 0x80600300 -#define CFG_PMI_UNI_BASE 0x80800000 -#define CFG_PMI_BROAD_BASE 0x80810000 - -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -# define CFG_RAMBOOT 1 -#endif - -#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_SYS_STATUS1_BASE 0x80600200 +#define CONFIG_SYS_STATUS2_BASE 0x80600300 +#define CONFIG_SYS_PMI_UNI_BASE 0x80800000 +#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000 /* * GPIO configuration */ -#define CFG_GPS_PORT_CONFIG 0x8D550644 - -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CFG_ALT_MEMTEST - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644 -/* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE -#else -#define CFG_HID0_INIT 0 -#define CFG_HID0_FINAL 0 -#endif +#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x0004FB00 -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 /* 8Mbit SRAM @0x80100000 */ -#define CFG_CS1_START 0x80100000 -#define CFG_CS1_SIZE 0x00100000 -#define CFG_CS1_CFG 0x00019B00 +#define CONFIG_SYS_CS1_SIZE 0x00100000 +#define CONFIG_SYS_CS1_CFG 0x00019B00 + +#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE /* FRAM 32Kbyte @0x80700000 */ -#define CFG_CS2_START 0x80700000 -#define CFG_CS2_SIZE 0x00008000 -#define CFG_CS2_CFG 0x00019800 +#define CONFIG_SYS_CS2_START 0x80700000 +#define CONFIG_SYS_CS2_SIZE 0x00008000 +#define CONFIG_SYS_CS2_CFG 0x00019800 /* Display H1, Status Inputs, EPLD @0x80600000 */ -#define CFG_CS3_START 0x80600000 -#define CFG_CS3_SIZE 0x00100000 -#define CFG_CS3_CFG 0x00019800 +#define CONFIG_SYS_CS3_START 0x80600000 +#define CONFIG_SYS_CS3_SIZE 0x00100000 +#define CONFIG_SYS_CS3_CFG 0x00019800 /* PMI Unicast 32Kbyte @0x80800000 */ -#define CFG_CS6_START CFG_PMI_UNI_BASE -#define CFG_CS6_SIZE 0x00008000 -#define CFG_CS6_CFG 0xFFFFF930 +#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE +#define CONFIG_SYS_CS6_SIZE 0x00008000 +#define CONFIG_SYS_CS6_CFG 0xFFFFF930 /* PMI Broadcast 32Kbyte @0x80810000 */ -#define CFG_CS7_START CFG_PMI_BROAD_BASE -#define CFG_CS7_SIZE 0x00008000 -#define CFG_CS7_CFG 0xFF00F930 - -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x33333333 +#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE +#define CONFIG_SYS_CS7_SIZE 0x00008000 +#define CONFIG_SYS_CS7_CFG 0xFF00F930 /*----------------------------------------------------------------------- * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CFG_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CFG_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CFG_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ /* * PCI Mapping: @@ -364,13 +130,13 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 -#define CFG_ISA_IO CONFIG_PCI_IO_BUS +#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS /*---------------------------------------------------------------------*/ /* Display addresses */ /*---------------------------------------------------------------------*/ -#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) -#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) +#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38) +#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30) #endif /* __CONFIG_H */