X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmaxbcm.h;h=db84302231a6dfeb12ca964557d70dee5fd7cdc9;hb=898bd53e6a930080cee7cd7b1a09120c4dfd9467;hp=073c5a57b2c9cc9f260e1f68a5d6ccc0c99cf8bd;hpb=9b72d934c2f7d8ee894f87e082577743877eb76e;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 073c5a5..db84302 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -46,24 +46,7 @@
  * L2 cache thus cannot be used.
  */
 
-/* SPL */
-/* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE		((128 << 10) - (CONFIG_SPL_TEXT_BASE - 0x40000000))
-
-#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
-#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
-
-#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
-#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
-
-/* SPL related SPI defines */
-
 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 #define CONFIG_SYS_SDRAM_SIZE		SZ_1G
-#define CONFIG_BOARD_ECC_SUPPORT	/* this board supports ECC */
 
 #endif /* _CONFIG_DB_MV7846MP_GP_H */