X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fmaxbcm.h;h=9cc13052cc75f5dcc43f70de8c042eaa15675d0e;hb=b9da77f1958aab4ec50ff2f095b40464ca2489dd;hp=325c8f7b459f2ea4f119e833fd1535a9480cebf2;hpb=e00f76cee906a48311d0c7c59b519b2e6a5c56f8;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 325c8f7..9cc1305 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2014 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_DB_MV7846MP_GP_H @@ -10,21 +9,17 @@ /* * High Level Configuration Options (easy to change) */ -#define CONFIG_DISPLAY_BOARDINFO_LATE /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TEXT_BASE 0x00800000 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* * Commands configuration */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#define CONFIG_CMD_ENV /* I2C */ #define CONFIG_SYS_I2C @@ -34,21 +29,11 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* SPI NOR flash default params, used by sf commands */ -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 /* Environment in SPI NOR flash */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ -#define CONFIG_PHY_MARVELL /* there is a marvell phy */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ -#define CONFIG_SYS_ALT_MEMTEST - /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros @@ -70,8 +55,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x40004030 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) @@ -85,10 +68,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */