X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fm53menlo.h;h=66591390d9030029870ee1c181f0f4723606b92f;hb=0ea156ba00f34b3b9c8735d25c8ec7b8dffffb45;hp=98fb2640bc6a92e57d3dcff6afc9f24a7dfa09d0;hpb=fd690a5e932010d0309a859169aeb77af94dff24;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h
index 98fb264..6659139 100644
--- a/include/configs/m53menlo.h
+++ b/include/configs/m53menlo.h
@@ -20,22 +20,13 @@
 #define PHYS_SDRAM_2_SIZE		(gd->bd->bi_dram[1].size)
 #define PHYS_SDRAM_SIZE			(gd->ram_size)
 
-#define CONFIG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
-#define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
-#define CONFIG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#define CFG_SYS_SDRAM_BASE		(PHYS_SDRAM_1)
+#define CFG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
+#define CFG_SYS_INIT_RAM_SIZE	(IRAM_SIZE)
 
 /*
  * U-Boot general configurations
  */
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
-#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
-						/* Boot argument buffer size */
 
 /*
  * Serial Driver
@@ -46,44 +37,34 @@
  * MMC Driver
  */
 #ifdef CONFIG_CMD_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
-#define CONFIG_SYS_FSL_ESDHC_NUM	1
+#define CFG_SYS_FSL_ESDHC_ADDR	0
 #endif
 
 /*
  * NAND
  */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE	1
-#define CONFIG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
+#define CFG_SYS_NAND_BASE		NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_REGS_BASE	NFC_BASE_ADDR_AXI
 #define CONFIG_MXC_NAND_IP_REGS_BASE	NFC_BASE_ADDR
-#define CONFIG_SYS_NAND_LARGEPAGE
+#define CFG_SYS_NAND_LARGEPAGE
 #define CONFIG_MXC_NAND_HWECC
-
-/* Environment is in NAND */
-#define CONFIG_ENV_RANGE		(0x00080000) /* 512 KiB */
 #endif
 
 /*
  * Ethernet on SOC (FEC)
  */
 #ifdef CONFIG_CMD_NET
-#define IMX_FEC_BASE			FEC_BASE_ADDR
 #define CONFIG_FEC_MXC_PHYADDR		0x0
-#define CONFIG_DISCOVER_PHY
-#define CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_ETHPRIME			"FEC0"
 #endif
 
-#define CONFIG_SYS_RTC_BUS_NUM		1 /* I2C2 */
+#define CFG_SYS_RTC_BUS_NUM		1 /* I2C2 */
 
 /*
  * RTC
  */
 #ifdef CONFIG_CMD_DATE
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	2000
+#define CFG_SYS_I2C_RTC_ADDR		0x68
 #endif
 
 /*
@@ -95,39 +76,12 @@
 #define CONFIG_MXC_USB_FLAGS		0
 #endif
 
-/*
- * SATA
- */
-#ifdef CONFIG_CMD_SATA
-#define CONFIG_DWC_AHSATA_PORT_ID	0
-#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_BASE_ADDR
-#define CONFIG_LBA48
-#endif
-
-/*
- * LCD
- */
-#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)
-
 /* LVDS display */
-#define CONFIG_SYS_LDB_CLOCK			33260000
-#define CONFIG_IMX_VIDEO_SKIP
-
-/* IIM Fuses */
-#define CONFIG_FSL_IIM
+#define CFG_SYS_LDB_CLOCK			33260000
 
 /* Watchdog */
 
 /*
- * NAND SPL
- */
-#define CONFIG_SPL_TARGET		"u-boot-with-nand-spl.imx"
-#define CONFIG_SPL_PAD_TO		0x8000
-#define CONFIG_SPL_STACK		0x70004000
-
-#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
-
-/*
  * Extra Environments
  */
 #define CONFIG_HOSTNAME		"m53menlo"
@@ -140,8 +94,6 @@
 	"mmcpart=1\0"							\
 	"rootpath=/srv/\0"						\
 	"kernel_addr_r=0x72000000\0"					\
-	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0"				\
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"			\
 	"netdev=eth0\0"							\
 	"splashsource=mmc_fs\0"						\
 	"splashfile=boot/usplash.bmp.gz\0"				\