X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Flx2160a_common.h;h=bbee9df404a1d77952ec28fec62505139c9a0fef;hb=65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8;hp=b7543731691fc41a70eec82d40e1b781eb481973;hpb=36b661dc919da318c163a45f4a220d2e3d9db608;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index b754373..bbee9df 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -10,19 +10,15 @@
 #include <asm/arch/config.h>
 #include <asm/arch/soc.h>
 
-#define CONFIG_FSL_MEMAC
-
-#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CFG_SYS_FLASH_BASE		0x20000000
 
 /* DDR */
-#define CONFIG_SYS_FSL_DDR_INTLV_256B	/* force 256 byte interleaving */
 #define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
-#define CONFIG_SYS_SDRAM_SIZE			0x200000000UL
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE		0x80000000UL
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CFG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
+#define CFG_SYS_SDRAM_SIZE			0x200000000UL
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #define SPD_EEPROM_ADDRESS1		0x51
 #define SPD_EEPROM_ADDRESS2		0x52
@@ -31,7 +27,6 @@
 #define SPD_EEPROM_ADDRESS5		0x55
 #define SPD_EEPROM_ADDRESS6		0x56
 #define SPD_EEPROM_ADDRESS		SPD_EEPROM_ADDRESS1
-#define CONFIG_SYS_MONITOR_LEN		(936 * 1024)
 
 /* Miscellaneous configurable options */
 
@@ -47,22 +42,22 @@
 
 /* Serial Port */
 #define CONFIG_PL011_CLOCK		(get_bus_freq(0) / 4)
-#define CONFIG_SYS_SERIAL0		0x21c0000
-#define CONFIG_SYS_SERIAL1		0x21d0000
-#define CONFIG_SYS_SERIAL2		0x21e0000
-#define CONFIG_SYS_SERIAL3		0x21f0000
+#define CFG_SYS_SERIAL0		0x21c0000
+#define CFG_SYS_SERIAL1		0x21d0000
+#define CFG_SYS_SERIAL2		0x21e0000
+#define CFG_SYS_SERIAL3		0x21f0000
 /*below might needs to be removed*/
-#define CONFIG_PL01x_PORTS		{(void *)CONFIG_SYS_SERIAL0, \
-					(void *)CONFIG_SYS_SERIAL1, \
-					(void *)CONFIG_SYS_SERIAL2, \
-					(void *)CONFIG_SYS_SERIAL3 }
+#define CONFIG_PL01x_PORTS		{(void *)CFG_SYS_SERIAL0, \
+					(void *)CFG_SYS_SERIAL1, \
+					(void *)CFG_SYS_SERIAL2, \
+					(void *)CFG_SYS_SERIAL3 }
 
 /* MC firmware */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
-#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH		0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET	0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH		0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET	0x00F20000
+#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS	5000
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -71,7 +66,7 @@
  * 512MB aligned, so the min size to hide is 512MB.
  */
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE	(256UL * 1024 * 1024)
 #endif
 
 /* I2C bus multiplexer */
@@ -80,14 +75,10 @@
 
 /* RTC */
 #define RTC
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
-
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CFG_SYS_I2C_RTC_ADDR		0x51  /* Channel 3*/
 
 /* Qixis */
-#define CONFIG_SYS_I2C_FPGA_ADDR		0x66
+#define CFG_SYS_I2C_FPGA_ADDR		0x66
 
 /* USB */