X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Flwmon5.h;h=cf406c8c0da6f5ea9c5bae5f696811c1418d680c;hb=776488eb88d0915945eeecfc1ad3e318979f9548;hp=4398b87ae1b13da4ad6dec682c089e435e593072;hpb=a1b215e2a2a013327693f2fb990957b746f26cf5;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 4398b87..cf406c8 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -75,8 +75,8 @@
 /*
  * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
  * the POST_WORD from OCM to a 440EPx register that preserves it's
- * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
- * for logbuffer only.
+ * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
+ * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
  */
 #define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
 #define CFG_INIT_RAM_ADDR	0x70000000		/* DCache       */
@@ -88,15 +88,20 @@
 						/* unused GPT0 COMP reg	*/
 #define CFG_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
 					/* 440EPx errata CHIP 11	*/
+#define CFG_OCM_SIZE		(16 << 10)
 
 /* Additional registers for watchdog timer post test */
 
-#define CFG_DSPIC_TEST_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
-#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP4)
-#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP5)
+#define CFG_WATCHDOG_TIME_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK2)
+#define CFG_WATCHDOG_FLAGS_ADDR	(CFG_PERIPHERAL_BASE + GPT0_MASK1)
+#define CFG_DSPIC_TEST_ADDR	CFG_WATCHDOG_FLAGS_ADDR
+#define CFG_OCM_STATUS_ADDR	CFG_WATCHDOG_FLAGS_ADDR
 #define CFG_WATCHDOG_MAGIC	0x12480000
 #define CFG_WATCHDOG_MAGIC_MASK	0xFFFF0000
 #define CFG_DSPIC_TEST_MASK	0x00000001
+#define CFG_OCM_STATUS_OK	0x00009A00
+#define CFG_OCM_STATUS_FAIL	0x0000A300
+#define CFG_OCM_STATUS_MASK	0x0000FF00
 
 /*-----------------------------------------------------------------------
  * Serial Port
@@ -162,6 +167,7 @@
 				 CFG_POST_FPU	   | \
 				 CFG_POST_I2C	   | \
 				 CFG_POST_MEMORY   | \
+				 CFG_POST_OCM      | \
 				 CFG_POST_RTC      | \
 				 CFG_POST_SPR      | \
 				 CFG_POST_UART     | \
@@ -242,6 +248,7 @@
 
 #define CFG_POST_CACHE_ADDR	0x7fff0000 /* free virtual address	*/
 #define CONFIG_LOGBUFFER
+/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
 #define CONFIG_ALT_LH_ADDR	(CFG_PERIPHERAL_BASE + GPT0_COMP1)
 #define CONFIG_ALT_LB_ADDR	(CFG_OCM_BASE)
 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
@@ -432,7 +439,6 @@
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_LOOPW            1       /* enable loopw command         */
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
 /*-----------------------------------------------------------------------
@@ -453,6 +459,7 @@
 
 #define CONFIG_HW_WATCHDOG	1	/* Use external HW-Watchdog	*/
 #define CONFIG_WD_PERIOD	40000	/* in usec */
+#define CONFIG_WD_MAX_RATE	66600	/* in ticks */
 
 /*
  * For booting Linux, the board info and command line data