X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080ardb.h;h=086c46902c865d12cabe5e4bc1b1cdc441b261b5;hb=4e5909450ec2acafb3d2e5b9714251ae67e0f0e0;hp=382d516c08bc1f50e3670cfda29bab072fdc1138;hpb=0cd03259644dcb967fcd6b31c3a92984125a1fe3;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 382d516..086c469 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -67,14 +67,14 @@
 					 CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
 
-#define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
-#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+#define CFG_SYS_NAND_CSPR_EXT	(0x0)
+#define CFG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
 				| CSPR_V)
-#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
+#define CFG_SYS_NAND_AMASK	IFC_AMASK(64 * 1024)
 
-#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+#define CFG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 				| CSOR_NAND_RAL_3	/* RAL = 3Byes */ \
@@ -83,20 +83,20 @@
 				| CSOR_NAND_PB(128))	/* Pages Per Block 128*/
 
 /* ONFI NAND Flash mode0 Timing Params */
-#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
+#define CFG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x0e) | \
 					FTIM0_NAND_TWP(0x30)   | \
 					FTIM0_NAND_TWCHT(0x0e) | \
 					FTIM0_NAND_TWH(0x14))
-#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
+#define CFG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x64) | \
 					FTIM1_NAND_TWBE(0xab)  | \
 					FTIM1_NAND_TRR(0x1c)   | \
 					FTIM1_NAND_TRP(0x30))
-#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
+#define CFG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x1e) | \
 					FTIM2_NAND_TREH(0x14) | \
 					FTIM2_NAND_TWHRE(0x3c))
-#define CONFIG_SYS_NAND_FTIM3		0x0
+#define CFG_SYS_NAND_FTIM3		0x0
 
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CFG_SYS_NAND_BASE_LIST	{ CFG_SYS_NAND_BASE }
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define QIXIS_LBMAP_SWITCH		0x06
@@ -146,16 +146,16 @@
 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
+#define CONFIG_SYS_CSPR0_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CFG_SYS_NAND_FTIM3
+
+#define CFG_SYS_NAND_U_BOOT_SIZE	(512 * 1024)
 #else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR_EARLY
@@ -166,14 +166,14 @@
 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CFG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CFG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CFG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CFG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CFG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CFG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CFG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CFG_SYS_NAND_FTIM3
 #endif
 #endif
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000