X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080aqds.h;h=c7146314dfee4fc9a71c9128da5075b8318db22b;hb=5d68d2f41df5099f890052756f14f5a810f34312;hp=f0c794d0fe099ea38c76c59aee9b3a3d7c58145f;hpb=efb5dab7ba8a9a6f89e44c4e60b0adb768c77e84;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index f0c794d..c714631 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -9,22 +9,13 @@ #include "ls2080a_common.h" -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -#endif - #ifdef CONFIG_FSL_QSPI -#define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_IFDR_DIV 0x7e #endif #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) +#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 @@ -33,23 +24,6 @@ unsigned long get_board_sys_clk(void); #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) @@ -93,17 +67,12 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif -#define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 @@ -122,8 +91,6 @@ unsigned long get_board_sys_clk(void); | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ -#define CONFIG_SYS_NAND_ONFI_DETECTION - /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ @@ -142,9 +109,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ #define QIXIS_LBMAP_SWITCH 0x06 #define QIXIS_LBMAP_MASK 0x0f #define QIXIS_LBMAP_SHIFT 0 @@ -215,8 +179,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) #endif #else @@ -265,15 +227,7 @@ unsigned long get_board_sys_clk(void); #define I2C_MUX_CH_DEFAULT 0x8 /* SPI */ -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON -#endif -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#endif /* * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 @@ -282,21 +236,11 @@ unsigned long get_board_sys_clk(void); #define FSL_QIXIS_BRDCFG9_QSPI 0x1 /* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - -/* * RTC configuration */ #define RTC #define CONFIG_RTC_DS3231 1 -#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT /* EEPROM */ #define CONFIG_SYS_I2C_EEPROM_NXID @@ -304,10 +248,6 @@ unsigned long get_board_sys_clk(void); #define CONFIG_FSL_MEMAC -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Initial environment variables */ #undef CONFIG_EXTRA_ENV_SETTINGS #ifdef CONFIG_NXP_ESBC @@ -451,7 +391,7 @@ unsigned long get_board_sys_clk(void); "env exists secureboot && esbc_halt;" #endif -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_FSL_MC_ENET) #define CONFIG_FSL_MEMAC #define SGMII_CARD_PORT1_PHY_ADDR 0x1C #define SGMII_CARD_PORT2_PHY_ADDR 0x1d @@ -475,8 +415,6 @@ unsigned long get_board_sys_clk(void); #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf -#define CONFIG_ETHPRIME "DPMAC1@xgmii" - #endif #include