X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080a_common.h;h=851db612d7c2c92d6a2d09ba2036a91fcd2d9d63;hb=a5d67547dd9c7a527dfda1967010e703a22441ff;hp=def0a6f3f09c1fa29d34dff93d4aa94aa92f80e0;hpb=161b1fe745394f34c4aa506edc964089785919f6;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index def0a6f..851db61 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -7,20 +7,14 @@ #ifndef __LS2_COMMON_H #define __LS2_COMMON_H - #define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH3 #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 - #include #include -#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) -#define CONFIG_SYS_HAS_SERDES -#endif /* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) @@ -28,12 +22,16 @@ /* We need architecture specific misc initializations */ #define CONFIG_ARCH_MISC_INIT +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* Link Definitions */ +#ifndef CONFIG_QSPI_BOOT #ifdef CONFIG_SPL #define CONFIG_SYS_TEXT_BASE 0x80400000 #else #define CONFIG_SYS_TEXT_BASE 0x30100000 #endif +#endif #ifdef CONFIG_EMU #define CONFIG_SYS_NO_FLASH @@ -42,22 +40,11 @@ #define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* Flat Device Tree Definitions */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ #ifndef CONFIG_SPL #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #endif #ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif @@ -98,7 +85,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) /* I2C */ -#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ @@ -110,7 +96,7 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) +#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } @@ -148,13 +134,6 @@ #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 -#ifndef CONFIG_SYS_NO_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - #ifndef __ASSEMBLY__ unsigned long long get_qixis_addr(void); #endif @@ -168,11 +147,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_BASE 0x530000000ULL #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 -/* Debug Server firmware */ -#define CONFIG_FSL_DEBUG_SERVER -/* 2 sec timeout */ -#define CONFIG_SYS_DEBUG_SERVER_TIMEOUT (2 * 1000 * 1000) - /* MC firmware */ #define CONFIG_FSL_MC_ENET /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ @@ -180,10 +154,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#ifdef CONFIG_LS2085A +/* For LS2085A */ #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 -#endif /* * Carve out a DDR region which will not be used by u-boot/Linux @@ -191,52 +164,16 @@ unsigned long long get_qixis_addr(void); * It will be used by MC and Debug Server. The MC region must be * 512MB aligned, so the min size to hide is 512MB. */ -#if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) -#define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) +#ifdef CONFIG_FSL_MC_ENET #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ -#define CONFIG_PCIE4 /* PCIE controler 4 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ -#ifdef CONFIG_LS2080A -#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie" -#endif - -#ifdef CONFIG_LS2085A -#define FSL_PCIE_COMPAT "fsl,ls2085a-pcie" -#endif - -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */ - /* Command line configuration */ -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DHCP #define CONFIG_CMD_ENV -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING /* Miscellaneous configurable options */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) -#define CONFIG_ARCH_EARLY_INIT_R /* Physical Memory Map */ /* fixme: these need to be checked against the board */ @@ -247,8 +184,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#define CONFIG_DISPLAY_CPUINFO - /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -264,22 +199,22 @@ unsigned long long get_qixis_addr(void); "kernel_start=0x581200000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyAMA0,38400n8\0" \ + "mcinitcmd=fsl_mc start mc 0x580300000" \ + " 0x580800000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" \ + "earlycon=uart8250,mmio,0x21c0500 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ - " hugepagesz=2m hugepages=16" -#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" -#define CONFIG_BOOTDELAY 10 + " hugepagesz=2m hugepages=256" +#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ + " cp.b $kernel_start $kernel_load" \ + " $kernel_size && bootm $kernel_load" /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING 1 @@ -290,17 +225,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0x1800a000 @@ -309,9 +236,14 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_LEN (640 * 1024) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif #endif /* __LS2_COMMON_H */