X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080a_common.h;h=770f2aaf6f99b7786dfe9cdc23b28788a72a95a7;hb=df6cf3d809fe543651e6bdf133baaa8b9841fe0f;hp=cc101fd01bd3a6ea8d7e1ca7bd27eb5bd7f51e28;hpb=1703fbefd9183fffd76f4744a73f5ca9daef6313;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index cc101fd..770f2aa 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -8,31 +8,21 @@ #define __LS2_COMMON_H #define CONFIG_REMAKE_ELF -#define CONFIG_FSL_LAYERSCAPE -#define CONFIG_GICV3 -#define CONFIG_FSL_TZPC_BP147 #include #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) +#endif /* We need architecture specific misc initializations */ /* Link Definitions */ -#ifndef CONFIG_QSPI_BOOT -#else -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif - -#define CONFIG_SKIP_LOWLEVEL_INIT -#ifndef CONFIG_SPL -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#endif #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #endif @@ -49,7 +39,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS #ifdef CONFIG_SYS_FSL_HAS_DP_DDR @@ -70,11 +60,14 @@ */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) +/* GPIO */ +#ifdef CONFIG_DM_GPIO +#ifndef CONFIG_MPC8XXX_GPIO +#define CONFIG_MPC8XXX_GPIO +#endif +#endif /* I2C */ -#define CONFIG_SYS_I2C /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL @@ -151,26 +144,18 @@ unsigned long long get_qixis_addr(void); * 512MB aligned, so the min size to hide is 512MB. */ #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) #endif -/* Command line configuration */ - /* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* Physical Memory Map */ /* fixme: these need to be checked against the board */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 3 - #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -187,6 +172,7 @@ unsigned long long get_qixis_addr(void); "mcinitcmd=fsl_mc start mc 0x580a00000" \ " 0x580e00000 \0" +#ifndef CONFIG_TFABOOT #ifdef CONFIG_SD_BOOT #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ " fsl_mc apply dpl 0x80200000 &&" \ @@ -197,6 +183,7 @@ unsigned long long get_qixis_addr(void); " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" #endif +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -207,7 +194,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SPL_MAX_SIZE 0x16000 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_TEXT_BASE 0x1800a000 #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000