X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1088aqds.h;h=747ee9d4428a796d4fdfd72a37194420d4937fa5;hb=b8e09898919e23c5d7f1934be7bf9a3a6f0deb0e;hp=5a33d3a128eeff373658cd8b1e180b7caa9d4204;hpb=388de0fa8bf5b232800b80ebb616363cda50f06c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 5a33d3a..747ee9d 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -9,18 +9,13 @@ #include "ls1088a_common.h" #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_QIXIS_I2C_ACCESS #define SYS_NO_FLASH -#else -#define CONFIG_QIXIS_I2C_ACCESS #endif #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -67,14 +62,8 @@ #define CONFIG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif @@ -116,7 +105,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_FSL_QIXIS #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 @@ -309,12 +297,6 @@ #endif #endif -#define CONFIG_FSL_MEMAC - -/* MMC */ -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - #define COMMON_ENV \ "kernelheader_addr_r=0x80200000\0" \ "fdtheader_addr_r=0x80100000\0" \ @@ -483,7 +465,6 @@ #endif #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_FSL_MEMAC #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C