X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1088aqds.h;h=747ee9d4428a796d4fdfd72a37194420d4937fa5;hb=b8e09898919e23c5d7f1934be7bf9a3a6f0deb0e;hp=3bfd1d2a86aa259c35317127c900ddf14d83849a;hpb=b77d0292ca9f3ca69259dca7e2c5e193a403b289;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 3bfd1d2..747ee9d 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2017, 2020 NXP + * Copyright 2017, 2020-2021 NXP */ #ifndef __LS1088A_QDS_H @@ -8,50 +8,14 @@ #include "ls1088a_common.h" - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_MISC_INIT_R -#else -#if defined(CONFIG_QSPI_BOOT) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#endif - #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_QIXIS_I2C_ACCESS #define SYS_NO_FLASH - -#undef CONFIG_CMD_IMLS -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#else -#define CONFIG_QIXIS_I2C_ACCESS -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C_EARLY_INIT -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() #endif -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4) -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* @@ -98,21 +62,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_IFC_CCR 0x01000000 #ifndef SYS_NO_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ CONFIG_SYS_FLASH_BASE + 0x40000000} #endif #endif -#define CONFIG_NAND_FSL_IFC #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 @@ -131,8 +87,6 @@ unsigned long get_board_ddr_clk(void); | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ -#define CONFIG_SYS_NAND_ONFI_DETECTION - /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ FTIM0_NAND_TWP(0x18) | \ @@ -150,11 +104,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_FSL_QIXIS #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 6 #define QIXIS_QMAP_MASK 0xe0 @@ -325,22 +275,10 @@ unsigned long get_board_ddr_clk(void); #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define I2C_SVDD_MONITOR_ADDR 0x4F -#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" -#define CONFIG_VID - /* The lowest and highest voltage allowed for LS1088AQDS */ #define VDD_MV_MIN 819 #define VDD_MV_MAX 1212 -#define CONFIG_VOL_MONITOR_LTC3882_SET -#define CONFIG_VOL_MONITOR_LTC3882_READ - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 - #define PWM_CHANNEL0 0x0 /* @@ -350,50 +288,27 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ /* EEPROM */ -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 - -#endif #ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON #if !defined(CONFIG_TFABOOT) && \ !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #endif #endif -#define CONFIG_CMD_MEMINFO - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#define CONFIG_FSL_MEMAC - -/* MMC */ -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) +#define COMMON_ENV \ + "kernelheader_addr_r=0x80200000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernel_addr_r=0x81000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" /* Initial environment variables */ #ifdef CONFIG_NXP_ESBC #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -404,7 +319,7 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ + "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \ "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ "sf read 0xa0e00000 0xe00000 0x100000;" \ "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ @@ -413,18 +328,19 @@ unsigned long get_board_ddr_clk(void); #else /* if !(CONFIG_NXP_ESBC) */ #ifdef CONFIG_TFABOOT #define QSPI_MC_INIT_CMD \ - "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \ + "sf read 0x80e00000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" + "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" #define IFC_MC_INIT_CMD \ "fsl_mc start mc 0x580A00000 0x580E00000\0" #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -438,9 +354,9 @@ unsigned long get_board_ddr_clk(void); "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernel_size_sd=0x14000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \ + "sf read 0x80e00000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" \ "BOARD=ls1088aqds\0" \ "scriptaddr=0x80000000\0" \ @@ -486,6 +402,7 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_QSPI_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -496,13 +413,14 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \ + "sf read 0x80e00000 0xE00000 0x100000;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #elif defined(CONFIG_SD_BOOT) #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x800\0" \ @@ -513,13 +431,14 @@ unsigned long get_board_ddr_clk(void); "kernel_start=0x8000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x14000\0" \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ + "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \ + "mmc read 0x80e00000 0x7000 0x800;" \ + "fsl_mc start mc 0x80a00000 0x80e00000\0" \ "mcmemsize=0x70000000 \0" #else /* NOR BOOT */ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ + COMMON_ENV \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x90100000\0" \ "kernel_addr=0x100000\0" \ @@ -546,7 +465,6 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FSL_MC_ENET -#define CONFIG_FSL_MEMAC #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C @@ -571,9 +489,6 @@ unsigned long get_board_ddr_clk(void); #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf -#define CONFIG_ETHPRIME "DPMAC1@xgmii" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ - #endif #define BOOT_TARGET_DEVICES(func) \