X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1088a_common.h;h=720a95d2f5394dcea14872c02ad9297d0e27701c;hb=4db386655a889b6466d2c3f40839ad21205c6d21;hp=7d76170bf7698fa34a253b3f367fcdbb21b20279;hpb=ec5b8804de3938ad8b4dc51d1cdce622640a14ff;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 7d76170..720a95d 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -27,13 +27,12 @@
 /* Link Definitions */
 
 /* Link Definitions */
-#define CONFIG_SYS_FSL_QSPI_BASE	0x20000000
+#define CFG_SYS_FSL_QSPI_BASE	0x20000000
 
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
-#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
+#define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
+#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
 /*
  * SMP Definitinos
  */
@@ -45,9 +44,7 @@
 
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE     1
-#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
+#define CFG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 
 /*
  * During booting, IFC is mapped at the region of 0x30000000.
@@ -66,18 +63,18 @@
  * 0x5_C000_0000..0x5_ffff_ffff	IFC CS1 1GB (NOR/Promjet)
  *
  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
- * CONFIG_SYS_FLASH_BASE has the final address (core view)
- * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
- * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
+ * CFG_SYS_FLASH_BASE has the final address (core view)
+ * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
+ * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_TEXT_BASE is linked to 0x30000000 for booting
  */
 
-#define CONFIG_SYS_FLASH_BASE			0x580000000ULL
-#define CONFIG_SYS_FLASH_BASE_PHYS		0x80000000
-#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
+#define CFG_SYS_FLASH_BASE			0x580000000ULL
+#define CFG_SYS_FLASH_BASE_PHYS		0x80000000
+#define CFG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 
-#define CONFIG_SYS_FLASH1_BASE_PHYS		0xC0000000
-#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
+#define CFG_SYS_FLASH1_BASE_PHYS		0xC0000000
+#define CFG_SYS_FLASH1_BASE_PHYS_EARLY	0x8000000
 
 #ifndef __ASSEMBLY__
 unsigned long long get_qixis_addr(void);
@@ -88,18 +85,18 @@ unsigned long long get_qixis_addr(void);
 #define QIXIS_BASE_PHYS_EARLY			0xC000000
 
 
-#define CONFIG_SYS_NAND_BASE			0x530000000ULL
-#define CONFIG_SYS_NAND_BASE_PHYS		0x30000000
+#define CFG_SYS_NAND_BASE			0x530000000ULL
+#define CFG_SYS_NAND_BASE_PHYS		0x30000000
 
 
 /* MC firmware */
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
-#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
-#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
-#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
-#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
-#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
+#define CFG_SYS_LS_MC_DPC_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
+#define CFG_SYS_LS_MC_DPL_MAX_LENGTH	    0x20000
+#define CFG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
+#define CFG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH	0x200000
+#define CFG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET	0x07000000
 
 /*
  * Carve out a DDR region which will not be used by u-boot/Linux
@@ -109,19 +106,18 @@ unsigned long long get_qixis_addr(void);
  */
 
 #if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
+#define CFG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE		(128UL * 1024 * 1024)
 #endif
 
 /* Miscellaneous configurable options */
 
 /* Physical Memory Map */
 
-#define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 
 #ifndef SPL_NO_ENV
 /* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS		\
+#define CFG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"loadaddr=0x80100000\0"			\
 	"kernel_addr=0x100000\0"		\
@@ -137,20 +133,4 @@ unsigned long long get_qixis_addr(void);
 	" 0x580e00000 \0"
 #endif
 
-#ifdef CONFIG_SPL
-#ifdef CONFIG_NXP_ESBC
-#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
-/*
- * HDR would be appended at end of image and copied to DDR along
- * with U-Boot image. Here u-boot max. size is 512K. So if binary
- * size increases then increase this size in case of secure boot as
- * it uses raw u-boot image instead of fit image.
- */
-#define CONFIG_SYS_MONITOR_LEN         (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
-#else
-#define CONFIG_SYS_MONITOR_LEN         0x100000
-#endif /* ifdef CONFIG_NXP_ESBC */
-
-#endif
-
 #endif /* __LS1088_COMMON_H */