X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1046ardb.h;h=77b50dbdad6a9d28ed21293c5a552e2532b5ef8f;hb=29d280c88a1ff331dce2d4c7a5aaf2402aa0fd8a;hp=67ee62608cdd496974a93017929d2c144dc3dd7d;hpb=f7244f2c4815aa80a7cd7e9ceaee1969a16acd47;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 67ee626..77b50db 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LS1046ARDB_H__ @@ -9,22 +8,14 @@ #include "ls1046a_common.h" -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_TEXT_BASE 0x82000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x40100000 -#endif - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_MISC_INIT_R #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 @@ -38,17 +29,21 @@ #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg -#endif - #ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg #ifdef CONFIG_EMMC_BOOT #define CONFIG_SYS_FSL_PBL_RCW \ board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg #else #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg #endif +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg +#define CONFIG_SYS_FSL_PBL_PBI \ + board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +#define CONFIG_SYS_UBOOT_BASE 0x40100000 +#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif #ifndef SPL_NO_IFC @@ -95,7 +90,6 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) @@ -166,30 +160,34 @@ #define CONFIG_ENV_OVERWRITE #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ +#else #if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (1024 * 1024) +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) #define CONFIG_ENV_SIZE 0x2000 #else -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ #endif +#endif +#define AQR105_IRQ_MASK 0x80000000 /* FMan */ #ifndef SPL_NO_FMAN -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#ifdef CONFIG_NET #define CONFIG_PHY_REALTEK -#define CONFIG_PHY_AQUANTIA -#define AQR105_IRQ_MASK 0x80000000 +#endif +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 @@ -198,8 +196,11 @@ #define FM1_10GEC1_PHY_ADDR 0x0 +#define FDT_SEQ_MACADDR_FROM_ENV + #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif + #endif /* QSPI device */ @@ -208,48 +209,25 @@ #define CONFIG_SPI_FLASH_SPANSION #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_BAR #endif #endif -/* USB */ -#ifndef SPL_NO_USB -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_HCD -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#endif +#ifndef SPL_NO_MISC +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else +#if defined(CONFIG_QSPI_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;;" +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" #endif - -/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SCSI - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) #endif - -#ifndef SPL_NO_MISC -#define CONFIG_BOOTCOMMAND "sf probe 0:0;sf read $kernel_load" \ - "$kernel_start $kernel_size;" \ - "bootm $kernel_load" - -#define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:1m(rcw)," \ - "15m(u-boot),48m(kernel.itb);" \ - "7e800000.flash:16m(nand_uboot)," \ - "48m(nand_kernel),448m(nand_free)" #endif #include