X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043ardb.h;h=deae7873588ee5d11a8819f4fdcb5df765d8bf5d;hb=d56b4b19744c314c26dc77585a7c7a9253d1487d;hp=8fa3bb3a64829451c5a3b96b712205a3c2ecf7cd;hpb=0ff27d4a94637d4b1937c625d33212375bd118d9;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 8fa3bb3..deae787 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -29,7 +29,9 @@
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
 #define CONFIG_FSL_DDR_BIST
+#ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#endif
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
@@ -88,7 +90,9 @@
 /*
  * NAND Flash Definitions
  */
+#ifndef SPL_NO_IFC
 #define CONFIG_NAND_FSL_IFC
+#endif
 
 #define CONFIG_SYS_NAND_BASE		0x7e800000
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
@@ -132,7 +136,7 @@
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
 #endif
 
 /*
@@ -211,6 +215,7 @@
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
 
 /* EEPROM */
+#ifndef SPL_NO_EEPROM
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM		0
@@ -218,39 +223,46 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#endif
 
 /*
  * Environment
  */
+#ifndef SPL_NO_ENV
 #define CONFIG_ENV_OVERWRITE
+#endif
 
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_ENV_OFFSET		(24 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
-#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_OFFSET		(3 * 1024 * 1024)
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0
 #define CONFIG_ENV_SIZE			0x2000
 #else
 #define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
 #endif
 
 /* FMan */
-#ifdef CONFIG_SYS_DPAA_FMAN
-#define CONFIG_FMAN_ENET
+#ifndef SPL_NO_FMAN
+#define AQR105_IRQ_MASK			0x40000000
+
+#ifdef CONFIG_NET
 #define CONFIG_PHYLIB
-#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
-
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_AQUANTIA
-#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
@@ -264,29 +276,30 @@
 
 #define CONFIG_ETHPRIME			"FM1@DTSEC3"
 #endif
+#endif
 
 /* QE */
-#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
-	!defined(CONFIG_QSPI_BOOT)
+#ifndef SPL_NO_QE
+#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT)
 #define CONFIG_U_QE
 #endif
-#define CONFIG_SYS_QE_FW_ADDR     0x60600000
+#endif
 
 /* USB */
+#ifndef SPL_NO_USB
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #endif
+#endif
 
 /* SATA */
+#ifndef SPL_NO_SATA
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_CMD_SCSI
-#ifndef CONFIG_CMD_FAT
-#define CONFIG_CMD_FAT
-#endif
 #ifndef CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT2
 #endif
@@ -297,6 +310,7 @@
 #define SCSI_VEND_ID 0x1b4b
 #define SCSI_DEV_ID  0x9170
 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
 
 #include <asm/fsl_secure_boot.h>