X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043ardb.h;h=a0d39878b85e59940d22ced906a82d1f088f6675;hb=29d280c88a1ff331dce2d4c7a5aaf2402aa0fd8a;hp=71c26bdcdab5c62de8a0336cb4ce1951afa6ff59;hpb=8ea05705a70135a94419b0d243666c1b51fe1f8d;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 71c26bd..a0d3987 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LS1043ARDB_H__ @@ -9,40 +8,24 @@ #include "ls1043a_common.h" -#if defined(CONFIG_FSL_LS_PPA) -#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT -#define SEC_FIRMWARE_ERET_ADDR_REVERT - -#define CONFIG_SYS_LS_PPA_FW_IN_XIP -#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP -#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000 -#endif -#endif - -#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x82000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x60100000 -#endif - #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_MISC_INIT_R #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_FSL_DDR_BIST -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#ifndef CONFIG_SPL #define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_FSL_DDR_BIST #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg @@ -54,6 +37,11 @@ #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg +#define CONFIG_CMD_SPL +#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 #endif /* @@ -98,7 +86,9 @@ /* * NAND Flash Definitions */ +#ifndef SPL_NO_IFC #define CONFIG_NAND_FSL_IFC +#endif #define CONFIG_SYS_NAND_BASE 0x7e800000 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE @@ -135,14 +125,13 @@ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) +#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif /* @@ -173,6 +162,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -210,6 +218,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -221,6 +230,7 @@ #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 /* EEPROM */ +#ifndef SPL_NO_EEPROM #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 @@ -228,39 +238,48 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +#endif /* * Environment */ +#ifndef SPL_NO_ENV #define CONFIG_ENV_OVERWRITE +#endif + +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #if defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif /* FMan */ -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#ifndef SPL_NO_FMAN +#define AQR105_IRQ_MASK 0x40000000 +#ifdef CONFIG_NET #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK -#define CONFIG_PHY_AQUANTIA -#define AQR105_IRQ_MASK 0x40000000 +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 @@ -274,34 +293,13 @@ #define CONFIG_ETHPRIME "FM1@DTSEC3" #endif - -/* QE */ -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ - !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE -#endif -#define CONFIG_SYS_QE_FW_ADDR 0x60600000 - -/* USB */ -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI -#define CONFIG_CMD_SCSI -#ifndef CONFIG_CMD_FAT -#define CONFIG_CMD_FAT -#endif +#ifndef SPL_NO_SATA #ifndef CONFIG_CMD_EXT2 #define CONFIG_CMD_EXT2 #endif -#define CONFIG_DOS_PARTITION -#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 2 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ @@ -309,6 +307,7 @@ #define SCSI_VEND_ID 0x1b4b #define SCSI_DEV_ID 0x9170 #define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} +#endif #include