X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043ardb.h;h=6d9cbc8c7df08aa1ceedcaba947632fec1177956;hb=0f9595b9fa68ed1634adddf989fd037909eec433;hp=b4b4d5e178fb6e2eddaba8976bad575cf7695038;hpb=2d5e6b4aac59d3a93773f19839fbb86d9e704fb7;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index b4b4d5e..6d9cbc8 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LS1043ARDB_H__ @@ -9,46 +8,21 @@ #include "ls1043a_common.h" -#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x82000000 -#else -#define CONFIG_SYS_TEXT_BASE 0x60100000 -#endif - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - #define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_MISC_INIT_R #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_SYS_SPD_BUS_NUM 0 #ifndef CONFIG_SPL #define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#define CONFIG_FSL_DDR_BIST -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg -#define CONFIG_CMD_SPL #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 #endif @@ -81,7 +55,6 @@ #define CONFIG_SYS_NOR_FTIM3 0 #define CONFIG_SYS_IFC_CCR 0x01000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ @@ -95,9 +68,6 @@ /* * NAND Flash Definitions */ -#ifndef SPL_NO_IFC -#define CONFIG_NAND_FSL_IFC -#endif #define CONFIG_SYS_NAND_BASE 0x7e800000 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE @@ -116,8 +86,6 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ @@ -135,11 +103,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) #endif @@ -171,6 +136,25 @@ #define CONFIG_SYS_CPLD_FTIM3 0x0 /* IFC Timing Params */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -208,6 +192,7 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 #endif +#endif #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR @@ -220,49 +205,19 @@ /* EEPROM */ #ifndef SPL_NO_EEPROM -#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif /* * Environment */ -#ifndef SPL_NO_ENV -#define CONFIG_ENV_OVERWRITE -#endif - -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif /* FMan */ #ifndef SPL_NO_FMAN #define AQR105_IRQ_MASK 0x40000000 -#ifdef CONFIG_NET -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#endif - #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_AQUANTIA - #define RGMII_PHY1_ADDR 0x1 #define RGMII_PHY2_ADDR 0x2 @@ -277,20 +232,8 @@ #endif #endif -/* QE */ -#ifndef SPL_NO_QE -#if !defined(CONFIG_NAND_BOOT) && !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE -#endif -#endif - /* SATA */ #ifndef SPL_NO_SATA -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI -#ifndef CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT2 -#endif #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 2 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \