X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043ardb.h;h=5e570cd5e8d70ef23133d9efee09c7d808661b53;hb=be62fbf376261ab3a4ed5db3bf54d5df9e216d9f;hp=7d113a0737ec68ab434ddcb6079c35e13f6e097d;hpb=1670c8c219f6e47de624b4ed557b5a995265cd40;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 7d113a0..5e570cd 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -9,9 +9,6 @@
 
 #include "ls1043a_common.h"
 
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0x82000000
 #else
@@ -27,12 +24,14 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 /* Physical Memory Map */
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		2
 
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
 #define CONFIG_FSL_DDR_BIST
+#ifndef CONFIG_SPL
 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
+#endif
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
@@ -91,7 +90,9 @@
 /*
  * NAND Flash Definitions
  */
+#ifndef SPL_NO_IFC
 #define CONFIG_NAND_FSL_IFC
+#endif
 
 #define CONFIG_SYS_NAND_BASE		0x7e800000
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
@@ -135,7 +136,7 @@
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PAD_TO		0x20000		/* block aligned */
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(1024 << 10)
 #endif
 
 /*
@@ -214,6 +215,7 @@
 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_CPLD_FTIM3
 
 /* EEPROM */
+#ifndef SPL_NO_EEPROM
 #define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM		0
@@ -221,21 +223,14 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
-
-/* DSPI */
-#define CONFIG_FSL_DSPI
-#ifdef CONFIG_FSL_DSPI
-#define CONFIG_CMD_SF
-#define CONFIG_DM_SPI_FLASH
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SF_DEFAULT_BUS		1
-#define CONFIG_SF_DEFAULT_CS		0
 #endif
 
 /*
  * Environment
  */
+#ifndef SPL_NO_ENV
 #define CONFIG_ENV_OVERWRITE
+#endif
 
 #if defined(CONFIG_NAND_BOOT)
 #define CONFIG_ENV_IS_IN_NAND
@@ -254,9 +249,9 @@
 #endif
 
 /* FMan */
+#ifndef SPL_NO_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_CMD_MII
 #define CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
@@ -264,6 +259,7 @@
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
@@ -277,18 +273,47 @@
 
 #define CONFIG_ETHPRIME			"FM1@DTSEC3"
 #endif
+#endif
+
+/* QE */
+#ifndef SPL_NO_QE
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
+	!defined(CONFIG_QSPI_BOOT)
+#define CONFIG_U_QE
+#endif
+#define CONFIG_SYS_QE_FW_ADDR     0x60600000
+#endif
 
 /* USB */
+#ifndef SPL_NO_USB
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
+#endif
+#endif
+
+/* SATA */
+#ifndef SPL_NO_SATA
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_CMD_SCSI
+#ifndef CONFIG_CMD_FAT
+#define CONFIG_CMD_FAT
+#endif
+#ifndef CONFIG_CMD_EXT2
 #define CONFIG_CMD_EXT2
 #endif
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		2
+#define CONFIG_SYS_SCSI_MAX_LUN			2
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#endif
+
+#include <asm/fsl_secure_boot.h>
 
 #endif /* __LS1043ARDB_H__ */