X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043aqds.h;h=52b47ad6704e4f7c29a042714b4411309b7d0a16;hb=504bf790da08db9b4a443566cf6ef577f9c7996a;hp=561a05a12ce8f5cf9ab0f3f824f861abd5efabb5;hpb=c14d4b0051df5f569fa33d9937af1db267ed6d34;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 561a05a..52b47ad 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __LS1043AQDS_H__ @@ -9,14 +8,6 @@ #include "ls1043a_common.h" -#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x82000000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_TEXT_BASE 0x40010000 -#else -#define CONFIG_SYS_TEXT_BASE 0x60100000 -#endif - #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); @@ -32,14 +23,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ - #define CONFIG_DDR_ECC #ifdef CONFIG_DDR_ECC #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER @@ -48,7 +36,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHYLIB #define CONFIG_PHY_VITESSE #define CONFIG_PHY_REALTEK #define CONFIG_PHYLIB_10G @@ -93,12 +80,7 @@ unsigned long get_board_ddr_clk(void); #endif /* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SCSI -#define CONFIG_DOS_PARTITION -#define CONFIG_BOARD_LATE_INIT /* EEPROM */ #define CONFIG_ID_EEPROM @@ -200,7 +182,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #endif @@ -211,10 +192,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_I2C_EARLY_INIT -#define CONFIG_SYS_NO_FLASH #endif /* @@ -267,6 +248,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR @@ -334,6 +349,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 #endif +#endif /* * I2C bus multiplexer @@ -365,7 +381,8 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212 /* QSPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -374,35 +391,15 @@ unsigned long get_board_ddr_clk(void); #endif #endif -/* USB */ -#define CONFIG_HAS_FSL_XHCI_USB -#ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#endif - /* * Miscellaneous configurable options */ -#define CONFIG_MISC_INIT_R -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff #define CONFIG_SYS_HZ 1000 -/* - * Stack sizes - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (30 * 1024) - #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) @@ -417,26 +414,31 @@ unsigned long get_board_ddr_clk(void); */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else #ifdef CONFIG_NAND_BOOT -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SECT_SIZE 0x20000 #define CONFIG_ENV_SIZE 0x20000 #endif +#endif #define CONFIG_CMDLINE_TAG