X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1043a_common.h;h=96fdd6417ed2510dd7ba2e1360ba390e7735005f;hb=19ea606109135c3d9892d86e1b1c2a8fb551cc1b;hp=67b5ea715e860f8508a69f8b3a42b8c50a9dbb12;hpb=9ebc54b8a67b4112e7978493d1d588b3f4e3069b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 67b5ea7..96fdd64 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -1,7 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright 2019-2020 NXP */ #ifndef __LS1043A_COMMON_H @@ -27,17 +27,17 @@ #endif #define CONFIG_REMAKE_ELF -#define CONFIG_FSL_LAYERSCAPE -#define CONFIG_MP #define CONFIG_GICV2 #include #include /* Link Definitions */ +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#else #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) - -#define CONFIG_SUPPORT_RAW_INITRD +#endif #define CONFIG_SKIP_LOWLEVEL_INIT @@ -47,7 +47,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ @@ -56,7 +56,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) @@ -65,10 +64,7 @@ /* SD boot SPL */ #ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x17000 #define CONFIG_SPL_STACK 0x1001e000 #define CONFIG_SPL_PAD_TO 0x1d000 @@ -79,7 +75,7 @@ #define CONFIG_SPL_BSS_START_ADDR 0x8f000000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) /* * HDR would be appended at end of image and copied to DDR along @@ -90,15 +86,12 @@ #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) #else #define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #endif /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PBL_PAD -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE @@ -108,9 +101,9 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#ifdef CONFIG_SECURE_BOOT +#ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ +#endif /* ifdef CONFIG_NXP_ESBC */ #ifdef CONFIG_U_BOOT_HDR_SIZE /* @@ -128,7 +121,8 @@ /* IFC */ #ifndef SPL_NO_IFC -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) +#if defined(CONFIG_TFABOOT) || \ + (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -141,9 +135,6 @@ #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 #ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #endif @@ -151,12 +142,16 @@ #endif /* I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif /* PCIe */ #ifndef SPL_NO_PCIE @@ -169,28 +164,19 @@ #endif #endif -/* Command line configuration */ - /* MMC */ #ifndef SPL_NO_MMC #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif #endif /* DSPI */ #ifndef SPL_NO_DSPI -#define CONFIG_FSL_DSPI #ifdef CONFIG_FSL_DSPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SF_DEFAULT_BUS 1 -#define CONFIG_SF_DEFAULT_CS 0 -#endif #endif #endif @@ -200,9 +186,14 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_TFABOOT +#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 +#define CONFIG_SYS_QE_FW_ADDR 0x940000 + + +#else #ifdef CONFIG_NAND_BOOT /* Store Fman ucode at offeset 0x900000(72 blocks). */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SD_BOOT) /* @@ -210,22 +201,16 @@ * about 1MB (2040 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4a08) +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) #elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 1000000 -#define CONFIG_ENV_SPI_MODE 0x03 #else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ #define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 #endif +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif @@ -238,11 +223,11 @@ #define HWCONFIG_BUFFER_SIZE 128 #ifndef SPL_NO_MISC -#include #ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(USB, usb, 0) + func(USB, usb, 0) \ + func(DHCP, dhcp, na) #include #endif @@ -258,6 +243,8 @@ "fdtheader_addr_r=0x80100000\0" \ "kernelheader_addr_r=0x80200000\0" \ "kernel_addr_r=0x81000000\0" \ + "kernel_start=0x1000000\0" \ + "kernelheader_start=0x800000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ "kernelheader_addr=0x60800000\0" \ @@ -283,24 +270,19 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ "env exists secureboot && load ${devtype} " \ "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ "&& esbc_validate ${scripthdraddr};" \ "source ${scriptaddr}\0" \ "qspi_bootcmd=echo Trying load from qspi..;" \ "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_start " \ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ "bootm $load_addr#$board\0" \ "nor_bootcmd=echo Trying load from nor..;" \ @@ -309,6 +291,12 @@ "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ "bootm $load_addr#$board\0" \ + "nand_bootcmd=echo Trying load from NAND..;" \ + "nand info; nand read $load_addr " \ + "$kernel_start $kernel_size; env exists secureboot " \ + "&& nand read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ "sd_bootcmd=echo Trying load from SD ..;" \ "mmcinfo; mmc read $load_addr " \ "$kernel_addr_sd $kernel_size_sd && " \ @@ -319,6 +307,16 @@ #undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ + "env exists secureboot && esbc_halt;" +#else #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;" @@ -330,18 +328,11 @@ "env exists secureboot && esbc_halt;" #endif #endif +#endif /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LONGHELP - -#ifndef SPL_NO_MISC -#ifndef CONFIG_CMDLINE_EDITING -#define CONFIG_CMDLINE_EDITING 1 -#endif -#endif -#define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */