X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1028aqds.h;h=769ece901c19e29bcf5335e4cbfba3c34adee46a;hb=4db386655a889b6466d2c3f40839ad21205c6d21;hp=fe20363e690f7e32de12ebbb6d6f93d112f10e47;hpb=efb5dab7ba8a9a6f89e44c4e60b0adb768c77e84;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h
index fe20363..769ece9 100644
--- a/include/configs/ls1028aqds.h
+++ b/include/configs/ls1028aqds.h
@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2019-2020 NXP
+ * Copyright 2019-2021 NXP
  */
 
 #ifndef __LS1028A_QDS_H
@@ -8,23 +8,16 @@
 
 #include "ls1028a_common.h"
 
-#define CONFIG_SYS_CLK_FREQ		100000000
-#define COUNTER_FREQUENCY_REAL		(CONFIG_SYS_CLK_FREQ / 4)
-
-/* DDR */
-#define CONFIG_DIMM_SLOTS_PER_CTLR		2
-
-#define CONFIG_QIXIS_I2C_ACCESS
+#define COUNTER_FREQUENCY_REAL		(get_board_sys_clk() / 4)
 
 /*
  * QIXIS Definitions
  */
-#define CONFIG_FSL_QIXIS
 
 #ifdef CONFIG_FSL_QIXIS
 #define QIXIS_BASE			0x7fb00000
 #define QIXIS_BASE_PHYS			QIXIS_BASE
-#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define CFG_SYS_I2C_FPGA_ADDR	0x66
 #define QIXIS_LBMAP_SWITCH		1
 #define QIXIS_LBMAP_MASK		0x0f
 #define QIXIS_LBMAP_SHIFT		5
@@ -42,52 +35,38 @@
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
 #define QIXIS_RST_FORCE_MEM		0x01
 
-#define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
-#define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
+#define CFG_SYS_FPGA_CSPR_EXT	(0x0)
+#define CFG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 					CSPR_PORT_SIZE_8 | \
 					CSPR_MSEL_GPCM | \
 					CSPR_V)
-#define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
-#define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
+#define CFG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
 					CSOR_NOR_NOR_MODE_AVD_NOR | \
 					CSOR_NOR_TRHZ_80)
 #endif
 
 /* RTC */
-#define CONFIG_SYS_RTC_BUS_NUM         1
+#define CFG_SYS_RTC_BUS_NUM         1
 #define I2C_MUX_CH_RTC                 0xB
 
 /* Store environment at top of flash */
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
 /* LPUART */
 #ifdef CONFIG_LPUART
-#define CONFIG_LPUART_32B_REG
 #define CFG_LPUART_MUX_MASK	0xf0
 #define CFG_LPUART_EN		0xf0
 #endif
 
 /* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
 
-#define CONFIG_SYS_SATA1			AHCI_BASE_ADDR1
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
-#define CONFIG_SYS_SCSI_MAX_LUN			1
-#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-						CONFIG_SYS_SCSI_MAX_LUN)
 #ifndef SPL_NO_ENV
-#undef CONFIG_EXTRA_ENV_SETTINGS
-#define CONFIG_EXTRA_ENV_SETTINGS \
+#undef CFG_EXTRA_ENV_SETTINGS
+#define CFG_EXTRA_ENV_SETTINGS \
 	"board=ls1028aqds\0" \
 	"hwconfig=fsl_ddr:bank_intlv=auto\0" \
 	"ramdisk_addr=0x800000\0" \
 	"ramdisk_size=0x2000000\0" \
-	"fdt_addr=0x00f00000\0" \
 	"kernel_addr=0x01000000\0" \
 	"scriptaddr=0x80000000\0" \
 	"scripthdraddr=0x80080000\0" \
@@ -108,7 +87,6 @@
 	"kernelhdr_addr_sd=0x3000\0" \
 	"kernelhdr_size_sd=0x10\0" \
 	"console=ttyS0,115200\0" \
-	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
 	BOOTENV \
 	"boot_scripts=ls1028aqds_boot.scr\0" \
 	"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \