X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021atwr.h;h=b48cd0062beb3224599e19bea8aa55f37aa8e28c;hb=c27269953b94d19b3fc7a21a1c3e19985507b94d;hp=90ae770eeffaa4087760a3ab594ffe04b6a7486b;hpb=645176d1d5c37c91ddb06c366678fbe302550387;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 90ae770..b48cd00 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -15,15 +15,9 @@
 
 #define CONFIG_SYS_FSL_CLK
 
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DEEP_SLEEP
-#ifdef CONFIG_DEEP_SLEEP
-#define CONFIG_SILENT_CONSOLE
-#endif
 
 /*
  * Size of malloc() pool
@@ -112,26 +106,13 @@
 #endif
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_ENV_SUPPORT
-#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_WATCHDOG_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8
 
 #ifdef CONFIG_SECURE_BOOT
-#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
 /*
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image.
  */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		(0x400 + \
-		(CONFIG_U_BOOT_HDR_SIZE / 512)
-#else
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400
+#define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
 #endif /* ifdef CONFIG_SECURE_BOOT */
 
 #define CONFIG_SPL_TEXT_BASE		0x10000000
@@ -178,8 +159,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_SYS_HAS_SERDES
-
 #define CONFIG_FSL_CAAM			/* Enable CAAM */
 
 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
@@ -315,7 +294,6 @@
 /*
  * MMC
  */
-#define CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_GENERIC_MMC
 
@@ -342,13 +320,9 @@
 #define CONFIG_FSL_DCU_FB
 
 #ifdef CONFIG_FSL_DCU_FB
-#define CONFIG_VIDEO
 #define CONFIG_CMD_BMP
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 #define CONFIG_FSL_DCU_SII9022A
 #define CONFIG_SYS_I2C_DVI_BUS_NUM	1
@@ -394,7 +368,6 @@
 #endif
 
 /* PCIe */
-#define CONFIG_PCI		/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
@@ -416,7 +389,6 @@
 #define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
 
 #ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI
 #endif
@@ -424,8 +396,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_ARMV7_NONSEC
-#define CONFIG_ARMV7_VIRT
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 #define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200