X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021atsn.h;h=3742203278358b0b136f87ef579a14acfa23bacd;hb=d2e5250be49fce4653689c41a5dc7e2d7e7ecf33;hp=20b67b02b175ff19db5182387650c528efdb8a55;hpb=49c8ef0e45a91ec894ef15e7d043dafe8f1c5efd;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 20b67b0..3742203 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,28 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2019 NXP Semiconductors + * Copyright 2016-2019 NXP * Copyright 2019 Vladimir Oltean */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - #define CONFIG_DEEP_SLEEP -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE /* XHCI Support - enabled by default */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_CLK_FREQ 100000000 - #define DDR_SDRAM_CFG 0x470c0008 #define DDR_CS0_BNDS 0x008000bf #define DDR_CS0_CONFIG 0x80014302 @@ -50,15 +41,7 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001 -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - "board/freescale/ls1021atsn/ls102xa_pbi.cfg" -#endif - #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" - #ifdef CONFIG_NXP_ESBC #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) #endif /* ifdef CONFIG_NXP_ESBC */ @@ -86,15 +69,12 @@ #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif -#define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL