X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aqds.h;h=e069467b53ea88ea6e135bc9b60047918fdbfe7b;hb=5d226cd0136c72f725a4c38747c187878243b620;hp=f3d3aa227123acc968920ffd208cae237e206fe3;hpb=a0e80c97c9ba1409c2370f6c8b2a4d6a48cdb15c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f3d3aa2..e069467 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -1,7 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ + * Copyright 2019 NXP */ #ifndef __CONFIG_H @@ -51,13 +51,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW \ board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg #endif -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 -#define CONFIG_SYS_TEXT_BASE 0x82000000 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ CONFIG_SYS_MONITOR_LEN) @@ -67,19 +64,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_TEXT_BASE 0x40100000 -#endif - #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 -#define CONFIG_SYS_TEXT_BASE 0x82000000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO @@ -94,17 +84,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x60100000 -#endif - -#define CONFIG_NR_DRAM_BANKS 1 - #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #ifndef CONFIG_SYS_FSL_DDR4 #define CONFIG_SYS_DDR_RAW_TIMING #endif @@ -120,12 +103,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ - !defined(CONFIG_QSPI_BOOT) -#define CONFIG_U_QE -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#endif - /* * IFC Definitions */ @@ -161,9 +138,6 @@ unsigned long get_board_ddr_clk(void); FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0 -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS @@ -348,7 +322,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_LPUART_32B_REG #else -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -359,12 +332,26 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ +#ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C +#else +#define CONFIG_I2C_SET_DEFAULT_BUS_NUM +#define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 +#endif #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + /* * I2C bus multiplexer */ @@ -375,41 +362,10 @@ unsigned long get_board_ddr_clk(void); /* * MMC */ -#define CONFIG_FSL_ESDHC - -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ /* DM SPI */ #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) #define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_DATAFLASH -#endif -#endif - -/* - * USB - */ -/* EHCI Support - disbaled by default */ -/*#define CONFIG_HAS_FSL_DR_USB*/ - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/*XHCI Support - enabled by default*/ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif /* @@ -428,10 +384,8 @@ unsigned long get_board_ddr_clk(void); /* * eTSEC */ -#define CONFIG_TSEC_ENET #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII #define CONFIG_MII_DEFAULT_TSEC 3 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" @@ -454,8 +408,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_PHY_REALTEK - #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2 @@ -478,7 +430,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -496,13 +447,11 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif @@ -510,11 +459,7 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_AUTO_COMPLETE - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_LOAD_ADDR 0x82000000 @@ -537,24 +482,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_MISC_INIT_R - #include #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */