X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aqds.h;h=994e6ca362c4fe4a935fdaf155a0f99c566f77bc;hb=8ccf98b1cfd2811e3121c719e294bdd8ebab1c45;hp=152954165cc802e978a68a653508e32b95474f2f;hpb=5aa03ddd7ff67dce143a5ea5dbaa85e6aaaab23f;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 1529541..994e6ca 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -51,14 +50,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW \ board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg #endif -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 -#define CONFIG_SYS_TEXT_BASE 0x82000000 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ CONFIG_SYS_MONITOR_LEN) @@ -68,20 +64,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_TEXT_BASE 0x40100000 -#endif - #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 #define CONFIG_SPL_STACK 0x1001d000 #define CONFIG_SPL_PAD_TO 0x1c000 -#define CONFIG_SYS_TEXT_BASE 0x82000000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO @@ -96,12 +85,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x60100000 -#endif - -#define CONFIG_NR_DRAM_BANKS 1 - #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -220,7 +203,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #endif @@ -351,7 +333,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_LPUART #define CONFIG_LPUART_32B_REG #else -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -368,6 +349,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + /* * I2C bus multiplexer */ @@ -378,7 +368,6 @@ unsigned long get_board_ddr_clk(void); /* * MMC */ -#define CONFIG_FSL_ESDHC /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) @@ -397,26 +386,6 @@ unsigned long get_board_ddr_clk(void); #endif /* - * USB - */ -/* EHCI Support - disbaled by default */ -/*#define CONFIG_HAS_FSL_DR_USB*/ - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/*XHCI Support - enabled by default*/ -#define CONFIG_HAS_FSL_XHCI_USB - -#ifdef CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -#endif - -/* * Video */ #ifdef CONFIG_VIDEO_FSL_DCU_FB @@ -432,10 +401,8 @@ unsigned long get_board_ddr_clk(void); /* * eTSEC */ -#define CONFIG_TSEC_ENET #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII #define CONFIG_MII_DEFAULT_TSEC 3 #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" @@ -458,8 +425,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ETHPRIME "eTSEC1" -#define CONFIG_PHY_GIGE -#define CONFIG_PHYLIB #define CONFIG_PHY_REALTEK #define CONFIG_HAS_ETH0 @@ -481,11 +446,9 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_SCAN_SHOW -#define CONFIG_CMD_PCI #endif #define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS @@ -517,13 +480,6 @@ unsigned long get_board_ddr_clk(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff @@ -550,27 +506,21 @@ unsigned long get_board_ddr_clk(void); #if defined(CONFIG_SD_BOOT) #define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #else -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_MISC_INIT_R - #include #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */