X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aqds.h;h=5c9b41f2e7e19e7e01c29d667891d2e1b9f04f84;hb=0ff27d4a94637d4b1937c625d33212375bd118d9;hp=3796395bd6771f57cb58533368a719e8bc76fea5;hpb=a212d6966bfcf393e82e44246d7dfb6de032e82a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 3796395..5c9b41f 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -9,20 +9,15 @@ #define CONFIG_LS102XA -#define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_SYS_FSL_CLK +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SYS_FSL_CLK #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DEEP_SLEEP -#if defined(CONFIG_DEEP_SLEEP) -#define CONFIG_SILENT_CONSOLE -#endif /* * Size of malloc() pool @@ -65,17 +60,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -103,15 +87,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -144,7 +119,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ #ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ #define CONFIG_SYS_DDR_RAW_TIMING #endif #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -159,8 +133,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif -#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */ #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ @@ -279,10 +251,19 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80 #define QIXIS_RST_CTL_RESET 0x44 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_CTL_SYS 0x5 +#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c +#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 +#define QIXIS_RST_FORCE_3 0x45 +#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 +#define QIXIS_PWR_CTL2 0x21 +#define QIXIS_PWR_CTL2_PCTL 0x2 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ @@ -411,11 +392,7 @@ unsigned long get_board_ddr_clk(void); /* * MMC */ -#define CONFIG_MMC #define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC - -#define CONFIG_DOS_PARTITION /* SPI */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) @@ -450,29 +427,19 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_HAS_FSL_XHCI_USB #define CONFIG_USB_XHCI_FSL -#define CONFIG_USB_XHCI_DWC3 -#define CONFIG_USB_XHCI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #endif -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) -#define CONFIG_USB_STORAGE -#endif - /* * Video */ #define CONFIG_FSL_DCU_FB #ifdef CONFIG_FSL_DCU_FB -#define CONFIG_VIDEO #define CONFIG_CMD_BMP -#define CONFIG_CFB_CONSOLE -#define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 @@ -527,29 +494,10 @@ unsigned long get_board_ddr_clk(void); #endif /* PCIe */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" - -#define CONFIG_SYS_PCI_64BIT - -#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 -#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ -#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 -#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ - -#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 -#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 -#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 -#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #ifdef CONFIG_PCI -#define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif @@ -557,8 +505,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING -#define CONFIG_ARMV7_NONSEC -#define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 @@ -569,7 +515,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_DEVICE_DISABLE -#define CONFIG_BOOTDELAY 3 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000