X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aqds.h;h=45665115f662a77e1029d3502f158d0d2030c2fb;hb=aec118ebe63f7f0ab60916f9906fb3cb680abf7a;hp=b655b7ea46cf17ebed510e91f07d844cc514dd97;hpb=ca8a329a1b7f3195ee56fee4c0906ee883383dfa;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index b655b7e..4566511 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,37 +10,14 @@ #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_STACK 0x1001d000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0xc0000 -#endif - #ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_STACK 0x1001d000 +#define CFG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE +#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 #endif #define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE @@ -67,31 +44,25 @@ CSPR_PORT_SIZE_16 | \ CSPR_MSEL_NOR | \ CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ +#define CFG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ +#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ FTIM0_NOR_TEADC(0x5) | \ FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ +#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1a) | \ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ +#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0xe) | \ FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 +#define CFG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} @@ -99,17 +70,17 @@ * NAND Flash Definitions */ -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CFG_SYS_NAND_BASE 0x7e800000 +#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CFG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \ | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_NAND \ | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ +#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ @@ -117,21 +88,20 @@ | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ +#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ +#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ FTIM1_NAND_TWBE(0x39) | \ FTIM1_NAND_TRR(0xe) | \ FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ +#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ FTIM2_NAND_TREH(0xa) | \ FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 +#define CFG_SYS_NAND_FTIM3 0x0 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } #endif /* @@ -186,30 +156,30 @@ #endif #if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -221,28 +191,28 @@ #else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK @@ -257,11 +227,7 @@ * Serial Port */ #ifndef CONFIG_LPUART -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CFG_SYS_NS16550_CLK get_serial_clock() #endif /* @@ -270,10 +236,6 @@ /* GPIO */ -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 - /* * I2C bus multiplexer */ @@ -309,26 +271,9 @@ #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 #define TSEC3_PHYIDX 0 - -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1b - -#ifdef CONFIG_FSL_SGMII_RISER -#define CONFIG_SYS_TBIPA_VALUE 8 -#endif - -#endif - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW #endif #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_HWCONFIG @@ -355,16 +300,10 @@ #define CONFIG_LS102XA_STREAM_ID -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - /* * Environment */ #include -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #endif