X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aiot.h;h=ec688741a07e9e1f80edba72efb64906e844daab;hb=bf2c48fa1a6e068f232d84aae43b5dad654a9017;hp=82ae3492a2f2605c7d9c1e69bf382f8ec40e705d;hpb=c5b9bf5518411c72a3763371049cfabeb5f16633;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h
index 82ae349..ec68874 100644
--- a/include/configs/ls1021aiot.h
+++ b/include/configs/ls1021aiot.h
@@ -42,15 +42,6 @@
 #define SDRAM_CFG_BI			0x00000001
 
 #ifdef CONFIG_SD_BOOT
-#define CONFIG_SPL_MAX_SIZE		0x1a000
-#define CONFIG_SPL_STACK		0x1001d000
-#define CONFIG_SPL_PAD_TO		0x1c000
-
-#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
-		CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
-#define CONFIG_SPL_BSS_START_ADDR	0x80100000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 #define CONFIG_SYS_MONITOR_LEN		0x80000
 #endif
 
@@ -106,18 +97,9 @@
 #define TSEC2_PHYIDX			0
 #endif
 
-/* PCIe */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-
 #define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
 
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
 #define CONFIG_PEN_ADDR_BIG_ENDIAN
-#define CONFIG_LAYERSCAPE_NS_ACCESS
 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
 
 #define CONFIG_HWCONFIG
@@ -136,11 +118,6 @@
 
 #define CONFIG_LS102XA_STREAM_ID
 
-#define CONFIG_SYS_INIT_SP_OFFSET \
-	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
 #include <asm/fsl_secure_boot.h>
 
 #endif