X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1012aqds.h;h=fb0d1ba6b27df4be14504fa335971ce3e80030d5;hb=e4b91f085d4259f187052ff724c80af38fc11b18;hp=af5f37cca3fbc726d59d7af57c0271e2cefdad70;hpb=b55c89ce0207d3a504238c1b8f268c56035656a3;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index af5f37c..fb0d1ba 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __LS1012AQDS_H__
@@ -12,10 +11,8 @@
 /* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
-#define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_SIZE		0x40000000
 #define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
@@ -77,9 +74,7 @@
 
 /* DSPI */
 #define CONFIG_FSL_DSPI1
-#define CONFIG_DEFAULT_SPI_BUS 1
 
-#define CONFIG_CMD_SPI
 #define MMAP_DSPI          DSPI1_BASE_ADDR
 
 #define CONFIG_SYS_DSPI_CTAR0   1
@@ -102,47 +97,18 @@
 				DSPI_CTAR_DT(0))
 #define CONFIG_SPI_FLASH_EON /* cs3 */
 
-#define CONFIG_SF_DEFAULT_SPEED      10000000
-#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
-#define CONFIG_SF_DEFAULT_BUS        1
-#define CONFIG_SF_DEFAULT_CS         0
-
-/*
-* USB
-*/
-/* EHCI Support - disbaled by default */
-/*#define CONFIG_HAS_FSL_DR_USB*/
-
-#ifdef CONFIG_HAS_FSL_DR_USB
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#endif
-
 /*  MMC  */
 #ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
-/* SATA */
-#define CONFIG_SCSI_AHCI_PLAT
-
-#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
-
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
-#define CONFIG_SYS_SCSI_MAX_LUN			1
-#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-						CONFIG_SYS_SCSI_MAX_LUN)
-
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 
 #define CONFIG_PCI_SCAN_SHOW
 
 #define CONFIG_CMD_MEMINFO
-#define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
 
-#define CONFIG_MISC_INIT_R
-
+#include <asm/fsl_secure_boot.h>
 #endif /* __LS1012AQDS_H__ */